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//
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//
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// Xilinx VHDL ROM generator
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// Xilinx VHDL ROM generator
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//
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//
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// Version : 0221
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// Version : 0241
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//
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//
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// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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//
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//
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// All rights reserved
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// All rights reserved
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//
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//
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// File history :
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// File history :
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//
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//
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// 0220 : Initial release
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// 0220 : Initial release
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//
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//
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// 0221 : Fixed block ROMs with partial bytes
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// 0221 : Fixed block ROMs with partial bytes
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//
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// 0241 : Updated for WebPack 5.1
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#include <stdio.h>
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#include <stdio.h>
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#include <string>
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#include <string>
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#include <vector>
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#include <vector>
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#include <iostream>
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#include <iostream>
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#define max __max
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#define max __max
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#endif
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#endif
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int main (int argc, char *argv[])
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int main (int argc, char *argv[])
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{
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{
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cerr << "Xilinx VHDL ROM generator by Daniel Wallner. Version 0221\n";
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cerr << "Xilinx VHDL ROM generator by Daniel Wallner. Version 0241\n";
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try
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try
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{
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{
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unsigned long aWidth;
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unsigned long aWidth;
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unsigned long dWidth;
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unsigned long dWidth;
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printf("\n\t\tS%s : LUT4\n\t\t\tport map (", argv[1]);
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printf("\n\t\tS%s : LUT4\n\t\t\tport map (", argv[1]);
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if (blockIter)
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if (blockIter)
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{
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{
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printf("s");
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printf("s");
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}
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}
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printf("D(I), A_r(0), A_r(1), A_r(2), A_r(3));");
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printf("WE => '0', WCLK => '0', D => '0', O => D(I), A0 => A_r(0), A1 => A_r(1), A2 => A_r(2), A3 => A_r(3));");
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printf("\n\tend generate;");
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printf("\n\tend generate;");
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}
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}
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if (selectIter > 1)
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if (selectIter > 1)
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{
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{
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printf("\n\n\tsiA_r <= to_integer(A_r(A'left downto 4));");
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printf("\n\n\tsiA_r <= to_integer(A_r(A'left downto 4));");
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printf("\n\n\tsG1: for I in 0 to %d generate", selectIter - 1);
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printf("\n\n\tsG1: for I in 0 to %d generate", selectIter - 1);
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printf("\n\t\tsG2: for J in 0 to %d generate", dWidth - 1);
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printf("\n\t\tsG2: for J in 0 to %d generate", dWidth - 1);
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printf("\n\t\t\tS%s : LUT4\n\t\t\t\tport map (sRAMOut(I)(J), A_r(0), A_r(1), A_r(2), A_r(3));", argv[1]);
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printf("\n\t\t\tS%s : RAM16X1S\n\t\t\t\tport map (WE => '0', WCLK => '0', D => '0', O => sRAMOut(I)(J), A0 => A_r(0), A1 => A_r(1), A2 => A_r(2), A3 => A_r(3));", argv[1]);
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printf("\n\t\tend generate;");
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printf("\n\t\tend generate;");
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if (z == 'z')
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if (z == 'z')
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{
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{
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printf("\n\t\t");
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printf("\n\t\t");
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if (blockIter)
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if (blockIter)
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if (blockIter == 1)
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if (blockIter == 1)
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{
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{
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printf("\n\n\tbG1: for J in 0 to %d generate", bytes - 1);
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printf("\n\n\tbG1: for J in 0 to %d generate", bytes - 1);
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printf("\n\t\tB%s : RAMB4_S8", argv[1]);
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printf("\n\t\tB%s : RAMB4_S8", argv[1]);
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printf("\n\t\t\tport map (\"00000000\", '1', '0', '0', Clk, A(8 downto 0), bRAMOut(7 + 8 * J downto 8 * J));", argv[1]);
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printf("\n\t\t\tport map (DI => \"00000000\", EN => '1', RST => '0', WE => '0', CLK => Clk, ADDR => A(8 downto 0), DO => bRAMOut(7 + 8 * J downto 8 * J));", argv[1]);
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printf("\n\tend generate;");
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printf("\n\tend generate;");
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printf("\n\n\t");
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printf("\n\n\t");
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if (selectIter)
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if (selectIter)
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{
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{
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printf("b");
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printf("b");
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if (blockIter > 1)
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if (blockIter > 1)
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{
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{
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printf("\n\n\tbiA_r <= to_integer(A_r(A'left downto 9));");
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printf("\n\n\tbiA_r <= to_integer(A_r(A'left downto 9));");
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printf("\n\n\tbG1: for I in %d to %d generate", blockTotal - blockIter, blockTotal - 1);
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printf("\n\n\tbG1: for I in %d to %d generate", blockTotal - blockIter, blockTotal - 1);
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printf("\n\t\tbG2: for J in 0 to %d generate", bytes - 1);
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printf("\n\t\tbG2: for J in 0 to %d generate", bytes - 1);
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printf("\n\t\t\tB%s : RAMB4_S8\n\t\t\t\tport map (\"00000000\", '1', '0', '0', Clk, A(8 downto 0), bRAMOut(I)(7 + 8 * J downto 8 * J));", argv[1]);
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printf("\n\t\t\tB%s : RAMB4_S8\n\t\t\t\tport map (DI => \"00000000\", EN => '1', RST => '0', WE => '0', CLK => Clk, ADDR => A(8 downto 0), DO => bRAMOut(I)(7 + 8 * J downto 8 * J));", argv[1]);
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printf("\n\t\tend generate;");
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printf("\n\t\tend generate;");
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if (z == 'z')
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if (z == 'z')
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{
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{
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printf("\n\t\t");
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printf("\n\t\t");
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if (selectIter)
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if (selectIter)
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