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-----------------------------------------------------------------------
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---- ----
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---- Present - a lightweight block cipher project ----
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---- ----
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---- This file is part of the Present - a lightweight block ----
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---- cipher project ----
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---- http://www.http://opencores.org/project,present ----
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---- ----
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---- Description: ----
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---- Inverse substitution layer of Present decoder. Simple ----
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---- logic. For more information see ----
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---- http://homes.esat.kuleuven.be/~abogdano/papers/ ----
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---- present_ches07.pdf ----
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---- To Do: ----
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---- ----
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---- Author(s): ----
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---- - Krzysztof Gajewski, gajos@opencores.org ----
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---- k.gajewski@gmail.com ----
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---- ----
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-----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and-or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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No newline at end of file
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entity slayer_inv is
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generic (
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w_4 : integer := 4
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);
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port (
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input : in std_logic_vector(w_4-1 downto 0);
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output : out std_logic_vector(w_4-1 downto 0)
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);
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end slayer_inv;
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architecture Behavioral of slayer_inv is
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begin
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output <= x"0" when input = x"C" else
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x"1" when input = x"5" else
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x"2" when input = x"6" else
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x"3" when input = x"B" else
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x"4" when input = x"9" else
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x"5" when input = x"0" else
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x"6" when input = x"A" else
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x"7" when input = x"D" else
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x"8" when input = x"3" else
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x"9" when input = x"E" else
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x"A" when input = x"F" else
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x"B" when input = x"8" else
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x"C" when input = x"4" else
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x"D" when input = x"7" else
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x"E" when input = x"1" else
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x"F" when input = x"2" else
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"ZZZZ";
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end Behavioral;
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