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-----------------------------------------------------------------------
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---- ----
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---- Present - a lightweight block cipher project ----
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---- ----
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---- This file is part of the Present - a lightweight block ----
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---- cipher project ----
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---- http://www.http://opencores.org/project,present ----
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---- ----
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---- Description: ----
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---- State machine for Present decoder. It is only part of ----
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---- "inverse Present", not key gen. For more informations see ----
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---- below. ----
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---- To Do: ----
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---- ----
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---- Author(s): ----
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---- - Krzysztof Gajewski, gajos@opencores.org ----
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---- k.gajewski@gmail.com ----
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---- ----
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-----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and-or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.kody.ALL;
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entity PresentDecStateMachine is
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generic (
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w_5 : integer := 5
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);
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port (
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clk, reset, start : in std_logic;
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ready, cnt_res, ctrl_mux, RegEn: out std_logic;
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num : in std_logic_vector (w_5-1 downto 0)
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);
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end PresentDecStateMachine;
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architecture Behavioral of PresentDecStateMachine is
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signal state : stany;
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signal next_state : stany;
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begin
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States : process(state, start, num)
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begin
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case state is
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---- Waiting for start
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when NOP =>
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ready <= '0';
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cnt_res <= '0';
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ctrl_mux <= '0';
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if (start = '1') then
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RegEn <= '1';
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next_state <= SM_START;
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else
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RegEn <= '0';
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next_state <= NOP;
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end if;
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-- Decoding
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when SM_START =>
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ready <= '0';
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cnt_res <= '1';
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if (start = '1') then
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-- control during first start
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if (num = "11111") then
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RegEn <= '1';
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ctrl_mux <= '1';
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next_state <= SM_START;
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-- last iteration
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elsif (num = "00000") then
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RegEn <= '0';
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ctrl_mux <= '1';
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next_state <= SM_READY;
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-- rest iterations
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else
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RegEn <= '1';
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ctrl_mux <= '1';
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next_state <= SM_START;
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end if;
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else
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RegEn <= '0';
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ctrl_mux <= '0';
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next_state <= NOP;
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end if;
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-- Decoding end
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when SM_READY =>
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cnt_res <= '0';
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RegEn <= '0';
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ready <= '1';
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if (start = '1') then
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ctrl_mux <= '1';
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next_state <= SM_READY;
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else
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ctrl_mux <= '0';
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next_state <= NOP;
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end if;
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end case;
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end process States;
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SM : process (clk, reset)
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begin
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if (reset = '1') then
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state <= NOP;
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elsif (clk'Event and clk = '1') then
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state <= next_state;
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end if;
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end process SM;
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end Behavioral;
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