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-----------------------------------------------------------------------
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---- ----
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---- Present - a lightweight block cipher project ----
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---- ----
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---- This file is part of the Present - a lightweight block ----
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---- cipher project ----
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---- http://www.http://opencores.org/project,present ----
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---- ----
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---- Description: ----
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---- Top level part of 'pure' Present decode with RS-232 ----
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---- communication with PC. It contains all suitable components ----
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---- with links between each others. For more informations see ----
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---- below and http://homes.esat.kuleuven.be/~abogdano/papers/ ----
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---- present_ches07.pdf ----
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---- To Do: ----
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---- ----
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---- Author(s): ----
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---- - Krzysztof Gajewski, gajos@opencores.org ----
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---- k.gajewski@gmail.com ----
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---- ----
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-----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and-or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity PresentDecodeComm is
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generic (
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w_2: integer := 2;
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w_4: integer := 4;
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w_5: integer := 5;
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w_64: integer := 64;
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w_80: integer := 80
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);
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port (
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DATA_RXD : in STD_LOGIC;
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CLK : in STD_LOGIC;
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RESET : in STD_LOGIC;
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DATA_TXD : out STD_LOGIC
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);
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end PresentDecodeComm;
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architecture Behavioral of PresentDecodeComm is
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-- Shift register is used for translation 8 bit input of RS-232 data (both RXD and TXD)
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-- 64 bit and 80 bit data in dependence of the data type (key, text, result). SM ocntrols it
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-- If data are not fully retrieved, last received data are shifted by 8 bits. This is repeated
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-- 8 times for text and output value (8 x 8 bits) or 10 times (10 x 8 bits) for key.
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-- Width of the word is fully configurable.
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component ShiftReg is
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generic (
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length_1 : integer := 8;
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length_2 : integer := w_64;
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internal_data : integer := w_64
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);
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port (
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input : in STD_LOGIC_VECTOR(length_1 - 1 downto 0);
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output : out STD_LOGIC_VECTOR(length_2 - 1 downto 0);
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en : in STD_LOGIC;
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shift : in STD_LOGIC;
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clk : in STD_LOGIC;
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reset : in STD_LOGIC
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);
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end component ShiftReg;
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-- Component given by Digilent in Eval board for RS-232 communication
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component Rs232RefComp is
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Port (
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TXD : out std_logic := '1';
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RXD : in std_logic;
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CLK : in std_logic; --Master Clock
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DBIN : in std_logic_vector (7 downto 0); --Data Bus in
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DBOUT : out std_logic_vector (7 downto 0); --Data Bus out
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RDA : inout std_logic; --Read Data Available
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TBE : inout std_logic := '1'; --Transfer Bus Empty
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RD : in std_logic; --Read Strobe
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WR : in std_logic; --Write Strobe
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PE : out std_logic; --Parity Error Flag
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FE : out std_logic; --Frame Error Flag
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OE : out std_logic; --Overwrite Error Flag
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RST : in std_logic := '0'); --Master Reset
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end component Rs232RefComp;
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-- Present decoder - nothing special
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component PresentFullDecoder is
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generic (
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w_64: integer := 64;
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w_80: integer := 80
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);
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port(
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ciphertext : in std_logic_vector(w_64 - 1 downto 0);
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key : in std_logic_vector(w_80 - 1 downto 0);
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plaintext : out std_logic_vector(w_64 - 1 downto 0);
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start, clk, reset : in std_logic;
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ready : out std_logic
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);
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end component PresentFullDecoder;
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-- State machine
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component PresentDecodeCommSM is
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port (
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clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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RDAsig : in STD_LOGIC;
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TBEsig : in STD_LOGIC;
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RDsig : out STD_LOGIC;
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WRsig : out STD_LOGIC;
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textDataEn : out STD_LOGIC;
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textDataShift : out STD_LOGIC;
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keyDataEn : out STD_LOGIC;
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keyDataShift : out STD_LOGIC;
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ciphDataEn : out STD_LOGIC;
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ciphDataShift : out STD_LOGIC;
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startSig : out STD_LOGIC;
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readySig : in STD_LOGIC
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);
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end component PresentDecodeCommSM;
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--Signals
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signal keyText : STD_LOGIC_VECTOR(w_80 - 1 downto 0);
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signal plaintext : STD_LOGIC_VECTOR(w_64 - 1 downto 0);
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signal ciphertext : STD_LOGIC_VECTOR(w_64 - 1 downto 0);
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signal dataTXD : STD_LOGIC_VECTOR(7 downto 0);
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signal dataRXD : STD_LOGIC_VECTOR(7 downto 0);
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signal RDAsig : STD_LOGIC;
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signal TBEsig : STD_LOGIC;
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signal RDsig : STD_LOGIC;
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signal WRsig : STD_LOGIC;
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signal PEsig : STD_LOGIC;
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signal FEsig : STD_LOGIC;
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signal OEsig : STD_LOGIC;
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signal keyDataEn : STD_LOGIC;
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signal keyDataShift : STD_LOGIC;
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signal textDataEn : STD_LOGIC;
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signal textDataShift : STD_LOGIC;
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signal ciphDataEn : STD_LOGIC;
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signal ciphDataShift : STD_LOGIC;
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signal startSig : STD_LOGIC;
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signal readySig : STD_LOGIC;
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begin
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-- Connections
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RS232 : Rs232RefComp
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Port map(
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TXD => DATA_TXD,
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RXD => DATA_RXD,
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CLK => clk,
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DBIN => dataTXD,
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DBOUT => dataRXD,
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RDA => RDAsig,
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TBE => TBEsig,
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RD => RDsig,
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WR => WRsig,
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PE => PEsig,
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FE => FEsig,
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OE => OEsig,
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RST => reset
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);
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textReg : ShiftReg
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generic map(
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length_1 => 8,
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length_2 => w_64,
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internal_data => w_64
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)
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port map(
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input => dataRXD,
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output => plaintext,
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en => textDataEn,
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shift => textDataShift,
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clk => clk,
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reset => reset
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);
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keyReg : ShiftReg
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generic map(
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length_1 => 8,
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length_2 => w_80,
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internal_data => w_80
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)
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port map(
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input => dataRXD,
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output => keyText,
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en => keyDataEn,
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shift => keyDataShift,
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clk => clk,
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reset => reset
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);
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present :PresentFullDecoder
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port map(
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ciphertext => plaintext,
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key => keyText,
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plaintext => ciphertext,
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start => startSig,
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clk => clk,
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reset => reset,
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ready => readySig
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);
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outReg : ShiftReg
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generic map(
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length_1 => w_64,
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length_2 => 8,
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internal_data => w_64
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)
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port map(
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input => ciphertext,
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output => dataTXD,
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en => ciphDataEn,
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shift => ciphDataShift,
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clk => clk,
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reset => reset
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);
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SM : PresentDecodeCommSM
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port map(
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clk => clk,
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reset => reset,
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RDAsig => RDAsig,
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TBEsig => TBEsig,
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RDsig => RDsig,
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WRsig => WRsig,
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textDataEn => textDataEn,
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textDataShift => textDataShift,
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keyDataEn => keyDataEn,
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keyDataShift => keyDataShift,
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ciphDataEn => ciphDataEn,
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ciphDataShift => ciphDataShift,
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startSig => startSig,
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readySig => readySig
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);
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end Behavioral;
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