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-----------------------------------------------------------------------
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---- ----
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---- Present - a lightweight block cipher project ----
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---- ----
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---- This file is part of the Present - a lightweight block ----
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---- cipher project ----
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---- http://www.http://opencores.org/project,present ----
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---- ----
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---- Description: ----
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---- Present decoder with suitable key generator for decoding ----
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---- (basing on given encode key). ----
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---- To Do: ----
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---- ----
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---- Author(s): ----
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---- - Krzysztof Gajewski, gajos@opencores.org ----
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---- k.gajewski@gmail.com ----
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---- ----
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-----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and-or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity PresentFullDecoder is
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generic (
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w_2: integer := 2;
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w_4: integer := 4;
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w_5: integer := 5;
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w_32: integer := 32;
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w_64: integer := 64;
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w_80: integer := 80
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);
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port(
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ciphertext : in std_logic_vector(w_64 - 1 downto 0);
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key : in std_logic_vector(w_80 - 1 downto 0);
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plaintext : out std_logic_vector(w_64 - 1 downto 0);
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start, clk, reset : in std_logic;
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ready : out std_logic
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);
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end PresentFullDecoder;
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architecture Behavioral of PresentFullDecoder is
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-- Key generator component
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component PresentEncKeyGen is
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generic (
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w_2: integer := 2;
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w_4: integer := 4;
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w_5: integer := 5;
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w_80: integer := 80
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);
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port(
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key : in std_logic_vector(w_80 - 1 downto 0);
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key_end : out std_logic_vector(w_80 - 1 downto 0);
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start, clk, reset : in std_logic;
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ready : out std_logic
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);
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end component PresentEncKeyGen;
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-- 'pure' Present decoder
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component PresentDec is
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generic (
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w_2: integer := 2;
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w_4: integer := 4;
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w_5: integer := 5;
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w_32: integer := 32;
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w_64: integer := 64;
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w_80: integer := 80
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);
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port(
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plaintext : in std_logic_vector(w_64 - 1 downto 0);
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key : in std_logic_vector(w_80 - 1 downto 0);
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ciphertext : out std_logic_vector(w_64 - 1 downto 0);
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start, clk, reset : in std_logic;
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ready : out std_logic
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);
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end component PresentDec;
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component FullDecoderSM is
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port(
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key_gen_start : out std_logic;
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key_gen_ready : in std_logic;
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decode_start : out std_logic;
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decode_ready : in std_logic;
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full_decoder_start :in std_logic;
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full_decoder_ready : out std_logic;
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clk, reset :in std_logic
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);
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end component FullDecoderSM;
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-- signals
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signal key_gen_output : std_logic_vector(w_80 - 1 downto 0);
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signal key_gen_start : std_logic;
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signal key_gen_ready : std_logic;
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signal decode_start : std_logic;
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signal decode_ready : std_logic;
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begin
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-- connections
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keyGen : PresentEncKeyGen
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port map(
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key => key,
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key_end => key_gen_output,
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start => key_gen_start,
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clk => clk,
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reset => reset,
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ready => key_gen_ready
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);
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decoder : PresentDec
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port map(
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plaintext => ciphertext,
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key => key_gen_output,
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ciphertext => plaintext,
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start => decode_start,
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clk => clk,
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reset => reset,
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ready => decode_ready
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);
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SM : FullDecoderSM
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port map(
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key_gen_start => key_gen_start,
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key_gen_ready => key_gen_ready,
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decode_start => decode_start,
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decode_ready => decode_ready,
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full_decoder_start => start,
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full_decoder_ready => ready,
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clk => clk,
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reset => reset
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);
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end Behavioral;
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