OpenCores
URL https://opencores.org/ocsvn/present/present/trunk

Subversion Repositories present

[/] [present/] [trunk/] [DecodeTesting/] [rtl/] [vhdl/] [counter.vhd] - Diff between revs 3 and 4

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 3 Rev 4
Line 1... Line 1...
 
-----------------------------------------------------------------------
 
----                                                               ----
 
---- Present - a lightweight block cipher project                  ----
 
----                                                               ----
 
---- This file is part of the Present - a lightweight block        ----
 
---- cipher project                                                ----
 
---- http://www.http://opencores.org/project,present               ----
 
----                                                               ----
 
---- Description:                                                  ----
 
----     Typical construction of 5bit counter. It is counting up.  ----
 
---- Nothing special.                                              ----
 
---- To Do:                                                        ----
 
----                                                               ----
 
---- Author(s):                                                    ----
 
---- - Krzysztof Gajewski, gajos@opencores.org                     ----
 
----                       k.gajewski@gmail.com                    ----
 
----                                                               ----
 
-----------------------------------------------------------------------
 
----                                                               ----
 
---- Copyright (C) 2013 Authors and OPENCORES.ORG                  ----
 
----                                                               ----
 
---- This source file may be used and distributed without          ----
 
---- restriction provided that this copyright statement is not     ----
 
---- removed from the file and that any derivative work contains   ----
 
---- the original copyright notice and the associated disclaimer.  ----
 
----                                                               ----
 
---- This source file is free software; you can redistribute it    ----
 
---- and-or modify it under the terms of the GNU Lesser General    ----
 
---- Public License as published by the Free Software Foundation;  ----
 
---- either version 2.1 of the License, or (at your option) any    ----
 
---- later version.                                                ----
 
----                                                               ----
 
---- This source is distributed in the hope that it will be        ----
 
---- useful, but WITHOUT ANY WARRANTY; without even the implied    ----
 
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR       ----
 
---- PURPOSE. See the GNU Lesser General Public License for more   ----
 
---- details.                                                      ----
 
----                                                               ----
 
---- You should have received a copy of the GNU Lesser General     ----
 
---- Public License along with this source; if not, download it    ----
 
---- from http://www.opencores.org/lgpl.shtml                      ----
 
----                                                               ----
 
-----------------------------------------------------------------------
 
library IEEE;
 
use IEEE.STD_LOGIC_1164.ALL;
 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
 
entity counter is
 
        generic (
 
                w_5 : integer := 5
 
        );
 
        port (
 
                clk, reset, cnt_res : in std_logic;
 
                num : out std_logic_vector (w_5-1 downto 0)
 
        );
 
end counter;
 
 
 
architecture Behavioral of counter is
 
        signal cnt : std_logic_vector(w_5-1 downto 0) := (others => '0');
 
        begin
 
                licznik : process (clk, reset, cnt)
 
                        begin
 
                                if (reset = '1') then
 
                                        cnt <= (others => '0');
 
                                elsif (clk'Event and clk = '1') then
 
                                        if (cnt_res = '1') then
 
                                                cnt <= cnt + 1;
 
                                        end if;
 
                                end if;
 
                        end process licznik;
 
                        num <= cnt;
 
        end Behavioral;
 
 
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.