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-----------------------------------------------------------------------
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---- ----
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---- Present - a lightweight block cipher project ----
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---- ----
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---- This file is part of the Present - a lightweight block ----
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---- cipher project ----
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---- http://www.http://opencores.org/project,present ----
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---- ----
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---- Description: ----
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---- Permutation layer of Present decoder. Simple signal ----
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---- mixing, but in inverse way as cipher. For more information see----
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---- http://homes.esat.kuleuven.be/~abogdano/papers/ ----
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---- present_ches07.pdf ----
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---- To Do: ----
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---- ----
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---- Author(s): ----
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---- - Krzysztof Gajewski, gajos@opencores.org ----
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---- k.gajewski@gmail.com ----
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---- ----
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-----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and-or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity pLayer_inv is
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generic(w_64 : integer := 64);
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port (
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input : in std_logic_vector(w_64-1 downto 0);
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output : out std_logic_vector(w_64-1 downto 0)
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);
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end pLayer_inv;
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architecture Behavioral of pLayer_inv is
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begin
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output(0) <= input(0);
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output(1) <= input(16);
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output(2) <= input(32);
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output(3) <= input(48);
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output(4) <= input(1);
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output(5) <= input(17);
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output(6) <= input(33);
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output(7) <= input(49);
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output(8) <= input(2);
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output(9) <= input(18);
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output(10) <= input(34);
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output(11) <= input(50);
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output(12) <= input(3);
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output(13) <= input(19);
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output(14) <= input(35);
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output(15) <= input(51);
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output(16) <= input(4);
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output(17) <= input(20);
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output(18) <= input(36);
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output(19) <= input(52);
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output(20) <= input(5);
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output(21) <= input(21);
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output(22) <= input(37);
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output(23) <= input(53);
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output(24) <= input(6);
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output(25) <= input(22);
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output(26) <= input(38);
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output(27) <= input(54);
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output(28) <= input(7);
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output(29) <= input(23);
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output(30) <= input(39);
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output(31) <= input(55);
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output(32) <= input(8);
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output(33) <= input(24);
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output(34) <= input(40);
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output(35) <= input(56);
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output(36) <= input(9);
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output(37) <= input(25);
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output(38) <= input(41);
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output(39) <= input(57);
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output(40) <= input(10);
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output(41) <= input(26);
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output(42) <= input(42);
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output(43) <= input(58);
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output(44) <= input(11);
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output(45) <= input(27);
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output(46) <= input(43);
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output(47) <= input(59);
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output(48) <= input(12);
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output(49) <= input(28);
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output(50) <= input(44);
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output(51) <= input(60);
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output(52) <= input(13);
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output(53) <= input(29);
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output(54) <= input(45);
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output(55) <= input(61);
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output(56) <= input(14);
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output(57) <= input(30);
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output(58) <= input(46);
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output(59) <= input(62);
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output(60) <= input(15);
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output(61) <= input(31);
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output(62) <= input(47);
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output(63) <= input(63);
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end Behavioral;
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