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-----------------------------------------------------------------------
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---- ----
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---- Present - a lightweight block cipher project ----
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---- ----
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---- This file is part of the Present - a lightweight block ----
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---- cipher project ----
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---- http://www.http://opencores.org/project,present ----
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---- ----
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---- Description: ----
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---- Substitution layer test bench of Present encoder. ----
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---- Nothing special. ----
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---- To Do: ----
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---- ----
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---- Author(s): ----
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---- - Krzysztof Gajewski, gajos@opencores.org ----
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---- k.gajewski@gmail.com ----
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---- ----
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-----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and-or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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-----------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.all;
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USE ieee.numeric_std.ALL;
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ENTITY sLayerTB IS
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END sLayerTB;
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ARCHITECTURE behavior OF sLayerTB IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT slayer
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PORT(
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input : IN std_logic_vector(3 downto 0);
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output : OUT std_logic_vector(3 downto 0)
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);
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END COMPONENT;
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--Inputs
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signal clk : std_logic := '0';
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signal reset : std_logic := '0';
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--BiDirs
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signal input : std_logic_vector(3 downto 0);
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signal output : std_logic_vector(3 downto 0);
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-- Clock period definitions
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constant clk_period : time := 1ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: slayer PORT MAP (
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input => input,
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output => output
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100ms.
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reset <= '1';
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wait for 100ns;
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reset <= '0';
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wait for clk_period;
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input <= x"0";
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wait for clk_period;
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input <= x"A";
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wait for clk_period;
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input <= x"F";
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wait for clk_period;
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-- insert stimulus here
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assert false severity failure;
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end process;
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END;
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