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-----------------------------------------------------------------------
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---- ----
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---- Present - a lightweight block cipher project ----
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---- ----
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---- This file is part of the Present - a lightweight block ----
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---- cipher project ----
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---- http://www.http://opencores.org/project,present ----
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---- ----
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---- Description: ----
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---- State machine of 'pure' Present cipher with RS-232 ----
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---- communication with PC. For more informations see below. ----
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---- To Do: ----
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---- ----
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---- Author(s): ----
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---- - Krzysztof Gajewski, gajos@opencores.org ----
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---- k.gajewski@gmail.com ----
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---- ----
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-----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and-or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use work.kody.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity PresentCommSM is
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port (
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clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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RDAsig : in STD_LOGIC;
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TBEsig : in STD_LOGIC;
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RDsig : out STD_LOGIC;
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WRsig : out STD_LOGIC;
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textDataEn : out STD_LOGIC;
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textDataShift : out STD_LOGIC;
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keyDataEn : out STD_LOGIC;
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keyDataShift : out STD_LOGIC;
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ciphDataEn : out STD_LOGIC;
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ciphDataShift : out STD_LOGIC;
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startSig : out STD_LOGIC;
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readySig : in STD_LOGIC
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);
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end PresentCommSM;
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architecture Behavioral of PresentCommSM is
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-- counter used for determine number of readed/sended data (key, text, result)
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component counter is
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generic (
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w_5 : integer := 5
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);
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port (
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clk, reset, cnt_res : in std_logic;
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num : out std_logic_vector (w_5-1 downto 0)
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);
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end component counter;
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-- signals
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signal state : stany_comm := NOP;
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signal next_state : stany_comm := NOP;
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-- modify for variable key size
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signal serialDataCtrCt : STD_LOGIC;
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signal serialDataCtrOut : STD_LOGIC_VECTOR(3 downto 0);
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signal serialDataCtrReset : STD_LOGIC;
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signal ctrReset : STD_LOGIC;
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-- DO NOT MODIFY!!!
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signal shiftDataCtrCt : STD_LOGIC;
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signal shiftDataCtrOut : STD_LOGIC_VECTOR(2 downto 0);
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begin
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-- In this state machine is determined, that firs data should be 64 bit text
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-- after text, key should appear. After receiving last byte of key, ciphertext
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-- is counted. And later it is sended back to PC.
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ctrReset <= serialDataCtrReset or reset;
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SM : process(state, RDAsig, TBEsig, shiftDataCtrOut, serialDataCtrOut, readySig)
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begin
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case state is
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-- No operation - waiting for incoming data
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when NOP =>
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RDsig <= '0';
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WRsig <= '0';
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textDataEn <= '0';
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textDataShift <= '0';
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keyDataEn <= '0';
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keyDataShift <= '0';
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ciphDataEn <= '0';
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ciphDataShift <= '0';
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startSig <= '0';
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serialDataCtrCt <= '0';
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shiftDataCtrCt <= '0';
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serialDataCtrReset <= '0';
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-- data has come
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if (RDAsig = '1') then
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next_state <= READ_DATA_TEXT;
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else
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next_state <= NOP;
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end if;
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-- Text data enable and read data
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when READ_DATA_TEXT =>
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RDsig <= '1';
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WRsig <= '0';
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textDataEn <= '1';
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textDataShift <= '0';
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keyDataEn <= '0';
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keyDataShift <= '0';
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ciphDataEn <= '0';
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ciphDataShift <= '0';
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startSig <= '0';
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-- counter of retrieved bytes
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serialDataCtrCt <= '1';
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shiftDataCtrCt <= '0';
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serialDataCtrReset <= '0';
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next_state <= DECODE_READ_TEXT;
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-- Data readed, stop counter and check if proper number of byte
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-- was readed
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when DECODE_READ_TEXT =>
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RDsig <= '0';
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WRsig <= '0';
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textDataEn <= '0';
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textDataShift <= '0';
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keyDataEn <= '0';
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keyDataShift <= '0';
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ciphDataEn <= '0';
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ciphDataShift <= '0';
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startSig <= '0';
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serialDataCtrCt <= '0';
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shiftDataCtrCt <= '0';
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-- 8 bytes should be readed
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if (serialDataCtrOut(3 downto 0) = "1000") then
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-- 8 bytes was readed
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next_state <= TEMP_STATE;
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else
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-- 8 bytes was not readed
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next_state <= MOVE_TEXT;
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end if;
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-- Reset counter for next reading
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when TEMP_STATE =>
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RDsig <= '0';
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WRsig <= '0';
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textDataEn <= '0';
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textDataShift <= '0';
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keyDataEn <= '0';
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keyDataShift <= '0';
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ciphDataEn <= '0';
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ciphDataShift <= '0';
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startSig <= '0';
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serialDataCtrCt <= '0';
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shiftDataCtrCt <= '0';
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serialDataCtrReset <= '1';
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next_state <= NOP_FOR_KEY;
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-- Here data are shfted in shift register - another shift counter are used
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when MOVE_TEXT =>
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RDsig <= '0';
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WRsig <= '0';
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textDataEn <= '0';
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textDataShift <= '1';
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keyDataEn <= '0';
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keyDataShift <= '0';
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ciphDataEn <= '0';
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ciphDataShift <= '0';
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startSig <= '0';
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serialDataCtrCt <= '0';
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shiftDataCtrCt <= '1';
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serialDataCtrReset <= '0';
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if (shiftDataCtrOut(2 downto 0) = "111") then
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next_state <= NOP;
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else
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next_state <= MOVE_TEXT;
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end if;
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-- "No operation 2" waiting for data - it could be optimized in way,
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-- that waiting for key and text could be the same state, but it was
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-- intentionally separated.
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when NOP_FOR_KEY =>
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RDsig <= '0';
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WRsig <= '0';
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textDataEn <= '0';
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textDataShift <= '0';
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keyDataEn <= '0';
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keyDataShift <= '0';
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ciphDataEn <= '0';
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ciphDataShift <= '0';
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startSig <= '0';
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serialDataCtrCt <= '0';
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shiftDataCtrCt <= '0';
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serialDataCtrReset <= '0';
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if (RDAsig = '1') then
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-- data has come
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next_state <= READ_DATA_KEY;
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else
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next_state <= NOP_FOR_KEY;
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end if;
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-- Key data enable and read data
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when READ_DATA_KEY =>
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RDsig <= '1';
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WRsig <= '0';
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textDataEn <= '0';
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textDataShift <= '0';
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keyDataEn <= '1';
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keyDataShift <= '0';
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ciphDataEn <= '0';
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ciphDataShift <= '0';
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startSig <= '0';
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-- counter of retrieved bytes
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serialDataCtrCt <= '1';
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shiftDataCtrCt <= '0';
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serialDataCtrReset <= '0';
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next_state <= DECODE_READ_KEY;
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-- Data readed, stop counter and check if proper number of byte
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-- was readed
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when DECODE_READ_KEY =>
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RDsig <= '0';
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WRsig <= '0';
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textDataEn <= '0';
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textDataShift <= '0';
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keyDataEn <= '0';
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keyDataShift <= '0';
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ciphDataEn <= '0';
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ciphDataShift <= '0';
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startSig <= '0';
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serialDataCtrCt <= '0';
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shiftDataCtrCt <= '0';
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serialDataCtrReset <= '0';
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-- 10 bytes should be readed
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if (serialDataCtrOut(3 downto 0) = "1010") then
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-- 10 bytes was readed
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next_state <= TEMP2_STATE;
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else
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-- 10 bytes was not readed
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next_state <= MOVE_KEY;
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end if;
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-- Reset counter for next reading
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when TEMP2_STATE =>
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RDsig <= '0';
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WRsig <= '0';
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textDataEn <= '0';
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textDataShift <= '0';
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keyDataEn <= '0';
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keyDataShift <= '0';
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ciphDataEn <= '0';
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ciphDataShift <= '0';
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startSig <= '0';
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serialDataCtrCt <= '0';
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shiftDataCtrCt <= '0';
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serialDataCtrReset <= '1';
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next_state <= PRESENT_ENCODE;
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-- Here data are shfted in shift register - another shift counter are used
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when MOVE_KEY =>
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RDsig <= '0';
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WRsig <= '0';
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textDataEn <= '0';
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textDataShift <= '0';
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keyDataEn <= '0';
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keyDataShift <= '1';
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ciphDataEn <= '0';
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ciphDataShift <= '0';
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startSig <= '0';
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serialDataCtrCt <= '0';
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shiftDataCtrCt <= '1';
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serialDataCtrReset <= '0';
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if (shiftDataCtrOut(2 downto 0) = "111") then
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next_state <= NOP_FOR_KEY;
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else
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next_state <= MOVE_KEY;
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end if;
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-- All suitable data was readed Present encode start
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when PRESENT_ENCODE =>
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RDsig <= '0';
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WRsig <= '0';
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textDataEn <= '0';
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textDataShift <= '0';
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keyDataEn <= '0';
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keyDataShift <= '0';
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ciphDataShift <= '0';
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startSig <= '1';
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serialDataCtrCt <= '0';
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shiftDataCtrCt <= '0';
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serialDataCtrReset <= '0';
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-- change state if Present result ready
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if (readySig = '1') then
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ciphDataEn <= '1';
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next_state <= WRITE_OUT;
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else
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ciphDataEn <= '0';
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next_state <= PRESENT_ENCODE;
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end if;
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-- similar control of writing result as during reading
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when WRITE_OUT =>
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RDsig <= '0';
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textDataEn <= '0';
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textDataShift <= '0';
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keyDataEn <= '0';
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keyDataShift <= '0';
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ciphDataEn <= '0';
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ciphDataShift <= '0';
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startSig <= '1';
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serialDataCtrCt <= '1';
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shiftDataCtrCt <= '0';
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serialDataCtrReset <= '0';
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if (serialDataCtrOut = "1000") then
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WRsig <= '0';
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next_state <= TEMP_OUT;
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else
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WRsig <= '1';
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next_state <= MOVE_OUT;
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end if;
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-- all data was sended - start new Present encode cycle
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when TEMP_OUT =>
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RDsig <= '0';
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WRsig <= '0';
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textDataEn <= '0';
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textDataShift <= '0';
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keyDataEn <= '0';
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keyDataShift <= '0';
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ciphDataEn <= '0';
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ciphDataShift <= '0';
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startSig <= '1';
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serialDataCtrCt <= '0';
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shiftDataCtrCt <= '0';
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serialDataCtrReset <= '1';
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next_state <= NOP;
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when MOVE_OUT =>
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if (TBEsig = '0') then
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RDsig <= '0';
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WRsig <= '0';
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textDataEn <= '0';
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textDataShift <= '0';
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keyDataEn <= '0';
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keyDataShift <= '0';
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ciphDataEn <= '0';
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ciphDataShift <= '0';
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startSig <= '1';
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serialDataCtrCt <= '0';
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shiftDataCtrCt <= '0';
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serialDataCtrReset <= '0';
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next_state <= MOVE_OUT;
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else
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RDsig <= '0';
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WRsig <= '0';
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textDataEn <= '0';
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textDataShift <= '0';
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keyDataEn <= '0';
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keyDataShift <= '0';
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ciphDataEn <= '0';
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ciphDataShift <= '1';
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startSig <= '1';
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serialDataCtrCt <= '0';
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shiftDataCtrCt <= '1';
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serialDataCtrReset <= '0';
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if (shiftDataCtrOut = "111") then
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next_state <= WRITE_OUT;
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else
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next_state <= MOVE_OUT;
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end if;
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end if;
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end case;
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end process SM;
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|
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state_modifier : process (clk, reset)
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begin
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if (clk = '1' and clk'Event) then
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if (reset = '1') then
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state <= NOP;
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else
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state <= next_state;
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end if;
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end if;
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end process state_modifier;
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|
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-- counter for controling number of bytes of readed data
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dataCounter : counter
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generic map(
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w_5 => 4
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)
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port map (
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cnt_res => serialDataCtrCt,
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num => serialDataCtrOut,
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clk => clk,
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reset => ctrReset
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);
|
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|
-- counter for controling number of shifted bits of readed data
|
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shiftCounter : counter
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generic map(
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w_5 => 3
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)
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port map (
|
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cnt_res => shiftDataCtrCt,
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num => shiftDataCtrOut,
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clk => clk,
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reset => reset
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);
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|
end Behavioral;
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No newline at end of file
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No newline at end of file
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