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[/] [present/] [trunk/] [PureTesting/] [rtl/] [vhdl/] [ShiftReg.vhd] - Diff between revs 4 and 20

Rev 4	Rev 20
Line 75...	Line 75...
`signal data : STD_LOGIC_VECTOR(internal_data - 1 downto 0);`	`signal data : STD_LOGIC_VECTOR(internal_data - 1 downto 0);`

`begin`	`begin`
`reg : process (clk, reset, data)`	`reg : process (clk, reset, data)`
`begin`	`begin`
`if (clk'event and clk = '1') then`
`if (reset = '1') then`	`if (reset = '1') then`
`data <= (others => '0');`	`data <= (others => '0');`
`elsif (en = '1') then`	`elsif (clk'event and clk = '1') then`
	`if (en = '1') then`
`data(internal_data - 1 downto internal_data - length_1) <= input;`	`data(internal_data - 1 downto internal_data - length_1) <= input;`
`else`	`else`
`if (shift = '1') then`	`if (shift = '1') then`
`data <= '0' & data(internal_data - 1 downto 1);`	`data <= '0' & data(internal_data - 1 downto 1);`
`end if;`	`end if;`