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[/] [ps2/] [tags/] [asyst_2/] [rtl/] [verilog/] [ps2_io_ctrl.v] - Diff between revs 2 and 13

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.1.1.1  2002/02/18 16:16:56  mihad
 
// Initial project import - working
 
//
//
//
 
 
// synopsys translate_off
// synopsys translate_off
`include "timescale.v"
`include "timescale.v"
// synopsys translate_on
// synopsys translate_on
 
 
module ps2_io_ctrl
module ps2_io_ctrl
(
(
    clk_i,
    clk_i,
    rst_i,
    rst_i,
    ps2_ctrl_kbd_clk_en_i_,
    ps2_ctrl_clk_en_i_,
    ps2_ctrl_kbd_data_en_i_,
    ps2_ctrl_data_en_i_,
    ps2_kbd_clk_pad_i,
    ps2_clk_pad_i,
    ps2_kbd_clk_pad_oe_o,
    ps2_clk_pad_oe_o,
    ps2_kbd_data_pad_oe_o,
    ps2_data_pad_oe_o,
    inhibit_kbd_if_i,
    inhibit_if_i,
    ps2_ctrl_kbd_clk_o
    ps2_ctrl_clk_o
);
);
 
 
input clk_i,
input clk_i,
      rst_i,
      rst_i,
      ps2_ctrl_kbd_clk_en_i_,
      ps2_ctrl_clk_en_i_,
      ps2_ctrl_kbd_data_en_i_,
      ps2_ctrl_data_en_i_,
      ps2_kbd_clk_pad_i,
      ps2_clk_pad_i,
      inhibit_kbd_if_i ;
      inhibit_if_i ;
 
 
output ps2_kbd_clk_pad_oe_o,
output ps2_clk_pad_oe_o,
       ps2_kbd_data_pad_oe_o,
       ps2_data_pad_oe_o,
       ps2_ctrl_kbd_clk_o ;
       ps2_ctrl_clk_o ;
 
 
reg    ps2_kbd_clk_pad_oe_o,
reg    ps2_clk_pad_oe_o,
       ps2_kbd_data_pad_oe_o ;
       ps2_data_pad_oe_o ;
 
 
always@(posedge clk_i or posedge rst_i)
always@(posedge clk_i or posedge rst_i)
begin
begin
    if ( rst_i )
    if ( rst_i )
    begin
    begin
        ps2_kbd_clk_pad_oe_o  <= #1 1'b0 ;
        ps2_clk_pad_oe_o  <= #1 1'b0 ;
        ps2_kbd_data_pad_oe_o <= #1 1'b0 ;
        ps2_data_pad_oe_o <= #1 1'b0 ;
    end
    end
    else
    else
    begin
    begin
        ps2_kbd_clk_pad_oe_o  <= #1 !ps2_ctrl_kbd_clk_en_i_ || inhibit_kbd_if_i ;
        ps2_clk_pad_oe_o  <= #1 !ps2_ctrl_clk_en_i_ || inhibit_if_i ;
        ps2_kbd_data_pad_oe_o <= #1 !ps2_ctrl_kbd_data_en_i_ ;
        ps2_data_pad_oe_o <= #1 !ps2_ctrl_data_en_i_ ;
    end
    end
end
end
 
 
reg inhibit_kbd_if_previous ;
reg inhibit_if_previous ;
always@(posedge clk_i or posedge rst_i)
always@(posedge clk_i or posedge rst_i)
begin
begin
    if ( rst_i )
    if ( rst_i )
        inhibit_kbd_if_previous <= #1 1'b1 ;
        inhibit_if_previous <= #1 1'b1 ;
    else
    else
        inhibit_kbd_if_previous <= #1 inhibit_kbd_if_i ;
        inhibit_if_previous <= #1 inhibit_if_i ;
end
end
 
 
assign ps2_ctrl_kbd_clk_o = ps2_kbd_clk_pad_i || ps2_kbd_clk_pad_oe_o && inhibit_kbd_if_previous ;
assign ps2_ctrl_clk_o = ps2_clk_pad_i || ps2_clk_pad_oe_o && inhibit_if_previous ;
endmodule // ps2_io_ctrl
endmodule // ps2_io_ctrl
 
 
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