| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2003/05/28 16:27:09 simons
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// Change the address width.
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//
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// Revision 1.5 2002/04/09 13:24:11 mihad
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// Revision 1.5 2002/04/09 13:24:11 mihad
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// Added mouse interface and everything for its handling, cleaned up some unused code
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// Added mouse interface and everything for its handling, cleaned up some unused code
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//
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//
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// Revision 1.4 2002/02/20 16:35:43 mihad
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// Revision 1.4 2002/02/20 16:35:43 mihad
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// Little/big endian changes continued
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// Little/big endian changes continued
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| Line 85... |
Line 88... |
rx_scancode_i,
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rx_scancode_i,
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rx_kbd_data_ready_i,
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rx_kbd_data_ready_i,
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rx_kbd_read_o,
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rx_kbd_read_o,
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translate_o,
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translate_o,
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ps2_kbd_clk_i,
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ps2_kbd_clk_i,
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devide_reg_o,
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inhibit_kbd_if_o
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inhibit_kbd_if_o
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`ifdef PS2_AUX
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`ifdef PS2_AUX
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,
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,
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wb_intb_o,
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wb_intb_o,
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| Line 109... |
Line 113... |
wb_stb_i,
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wb_stb_i,
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wb_we_i ;
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wb_we_i ;
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input [3:0] wb_sel_i ;
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input [3:0] wb_sel_i ;
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input [2:0] wb_adr_i ;
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input [3:0] wb_adr_i ;
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input [31:0] wb_dat_i ;
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input [31:0] wb_dat_i ;
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output [31:0] wb_dat_o ;
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output [31:0] wb_dat_o ;
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| Line 139... |
Line 143... |
output inhibit_kbd_if_o ;
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output inhibit_kbd_if_o ;
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reg [7:0] input_buffer,
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reg [7:0] input_buffer,
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output_buffer ;
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output_buffer ;
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reg [7:0] wb_dat_i_sampled ;
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output [15:0] devide_reg_o;
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reg [15:0] devide_reg;
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assign devide_reg_o = devide_reg;
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reg [15:0] wb_dat_i_sampled ;
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always@(posedge wb_clk_i or posedge wb_rst_i)
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always@(posedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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if ( wb_rst_i )
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if ( wb_rst_i )
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wb_dat_i_sampled <= #1 0 ;
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wb_dat_i_sampled <= #1 0 ;
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else if ( wb_cyc_i && wb_stb_i && wb_we_i )
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else if ( wb_cyc_i && wb_stb_i && wb_we_i )
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wb_dat_i_sampled <= #1 wb_dat_i[31:24] ;
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wb_dat_i_sampled <= #1 wb_dat_i[31:16] ;
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end
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end
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`ifdef PS2_AUX
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`ifdef PS2_AUX
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output wb_intb_o ;
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output wb_intb_o ;
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reg wb_intb_o ;
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reg wb_intb_o ;
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| Line 190... |
Line 199... |
wire perr = 1'b0 ;
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wire perr = 1'b0 ;
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wire [7:0] status_byte = {perr, timeout, aux_input_buffer_full, kbd_inhibit, a2, system_flag, output_buffer_full || aux_output_buffer_full, input_buffer_full} ;
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wire [7:0] status_byte = {perr, timeout, aux_input_buffer_full, kbd_inhibit, a2, system_flag, output_buffer_full || aux_output_buffer_full, input_buffer_full} ;
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reg read_input_buffer_reg ;
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reg read_input_buffer_reg ;
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wire read_input_buffer = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !read_input_buffer_reg && !wb_we_i && (wb_adr_i[2:0] == 3'h0) ;
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wire read_input_buffer = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !read_input_buffer_reg && !wb_we_i && (wb_adr_i[3:0] == 4'h0) ;
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reg write_output_buffer_reg ;
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reg write_output_buffer_reg ;
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wire write_output_buffer = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !write_output_buffer_reg && wb_we_i && (wb_adr_i[2:0] == 3'h0) ;
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wire write_output_buffer = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !write_output_buffer_reg && wb_we_i && (wb_adr_i[3:0] == 4'h0) ;
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reg read_status_register_reg ;
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reg read_status_register_reg ;
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wire read_status_register = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !read_status_register_reg && !wb_we_i && (wb_adr_i[2:0] == 3'h4) ;
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wire read_status_register = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !read_status_register_reg && !wb_we_i && (wb_adr_i[3:0] == 4'h4) ;
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reg send_command_reg ;
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reg send_command_reg ;
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wire send_command = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !send_command_reg && wb_we_i && (wb_adr_i[2:0] == 3'h4) ;
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wire send_command = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !send_command_reg && wb_we_i && (wb_adr_i[3:0] == 4'h4) ;
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reg write_devide_reg ;
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wire write_devide = wb_cyc_i && wb_stb_i && wb_sel_i[3] && wb_sel_i[2] && !wb_ack_o && !write_devide_reg && wb_we_i && (wb_adr_i[3:0] == 4'h8) ;
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reg read_devide_reg ;
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wire read_devide = wb_cyc_i && wb_stb_i && wb_sel_i[3] && wb_sel_i[2] && !wb_ack_o && !read_devide_reg && !wb_we_i && (wb_adr_i[3:0] == 4'h8) ;
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reg translate_o,
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reg translate_o,
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enable1,
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enable1,
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system,
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system,
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interrupt1 ;
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interrupt1 ;
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reg inhibit_kbd_if_o ;
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reg inhibit_kbd_if_o ;
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always@(posedge wb_clk_i or posedge wb_rst_i)
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always@(posedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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if ( wb_rst_i )
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if ( wb_rst_i )
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inhibit_kbd_if_o <= #1 1'b1 ;
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inhibit_kbd_if_o <= #1 1'b0 ;
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else if ( ps2_kbd_clk_i && rx_kbd_data_ready_i && !enable1)
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else if ( ps2_kbd_clk_i && rx_kbd_data_ready_i && !enable1)
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inhibit_kbd_if_o <= #1 1'b1 ;
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inhibit_kbd_if_o <= #1 1'b1 ;
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else if ( !rx_kbd_data_ready_i || enable1 )
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else if ( !rx_kbd_data_ready_i || enable1 )
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inhibit_kbd_if_o <= #1 1'b0 ;
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inhibit_kbd_if_o <= #1 1'b0 ;
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| Line 246... |
Line 260... |
begin
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begin
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send_command_reg <= #1 1'b0 ;
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send_command_reg <= #1 1'b0 ;
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read_input_buffer_reg <= #1 1'b0 ;
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read_input_buffer_reg <= #1 1'b0 ;
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write_output_buffer_reg <= #1 1'b0 ;
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write_output_buffer_reg <= #1 1'b0 ;
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read_status_register_reg <= #1 1'b0 ;
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read_status_register_reg <= #1 1'b0 ;
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write_devide_reg <= #1 1'b0 ;
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read_devide_reg <= #1 1'b0 ;
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end
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end
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else
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else
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begin
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begin
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send_command_reg <= #1 send_command ;
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send_command_reg <= #1 send_command ;
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read_input_buffer_reg <= #1 read_input_buffer ;
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read_input_buffer_reg <= #1 read_input_buffer ;
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write_output_buffer_reg <= #1 write_output_buffer ;
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write_output_buffer_reg <= #1 write_output_buffer ;
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read_status_register_reg <= #1 read_status_register ;
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read_status_register_reg <= #1 read_status_register ;
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write_devide_reg <= #1 write_devide ;
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read_devide_reg <= #1 read_devide ;
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end
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end
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end
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end
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always@(posedge wb_clk_i or posedge wb_rst_i)
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always@(posedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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if ( wb_rst_i )
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if ( wb_rst_i )
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current_command <= #1 8'h0 ;
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current_command <= #1 8'h0 ;
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else if ( send_command_reg )
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else if ( send_command_reg )
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current_command <= #1 wb_dat_i_sampled ;
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current_command <= #1 wb_dat_i_sampled[15:8] ;
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end
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end
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reg current_command_valid,
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reg current_command_valid,
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current_command_returns_value,
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current_command_returns_value,
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current_command_gets_parameter,
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current_command_gets_parameter,
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| Line 448... |
Line 466... |
end
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end
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reg [31:0] wb_dat_o ;
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reg [31:0] wb_dat_o ;
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wire wb_read = read_input_buffer_reg || read_status_register_reg ;
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wire wb_read = read_input_buffer_reg || read_status_register_reg ;
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wire [7:0] output_data = read_status_register_reg ? status_byte : input_buffer ;
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wire [15:0] output_data = read_status_register_reg ? {2{status_byte}} : read_devide_reg ? devide_reg : {2{input_buffer}} ;
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always@(posedge wb_clk_i or posedge wb_rst_i)
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always@(posedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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if ( wb_rst_i )
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if ( wb_rst_i )
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wb_dat_o <= #1 32'h0 ;
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wb_dat_o <= #1 32'h0 ;
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else if ( wb_read )
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else if ( wb_read )
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wb_dat_o <= #1 {4{output_data}} ;
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wb_dat_o <= #1 {2{output_data}} ;
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end
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end
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always@(posedge wb_clk_i or posedge wb_rst_i)
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always@(posedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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if ( wb_rst_i )
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if ( wb_rst_i )
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| Line 484... |
Line 502... |
always@(posedge wb_clk_i or posedge wb_rst_i)
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always@(posedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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if ( wb_rst_i )
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if ( wb_rst_i )
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output_buffer <= #1 8'h00 ;
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output_buffer <= #1 8'h00 ;
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else if ( write_output_buffer_reg )
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else if ( write_output_buffer_reg )
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output_buffer <= #1 wb_dat_i_sampled ;
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output_buffer <= #1 wb_dat_i_sampled[15:8];
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end
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always@(posedge wb_clk_i or posedge wb_rst_i)
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begin
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if ( wb_rst_i )
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devide_reg <= #1 8'h00 ;
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else if ( write_devide_reg )
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devide_reg <= #1 wb_dat_i_sampled ;
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end
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end
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always@(posedge wb_clk_i or posedge wb_rst_i)
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always@(posedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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if ( wb_rst_i )
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if ( wb_rst_i )
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