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Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2003/10/03 10:16:52 primozs
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// support for configurable devider added
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//
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// Revision 1.6 2003/05/28 16:27:09 simons
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// Revision 1.6 2003/05/28 16:27:09 simons
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// Change the address width.
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// Change the address width.
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//
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//
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// Revision 1.5 2002/04/09 13:24:11 mihad
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// Revision 1.5 2002/04/09 13:24:11 mihad
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// Added mouse interface and everything for its handling, cleaned up some unused code
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// Added mouse interface and everything for its handling, cleaned up some unused code
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Line 213... |
wire read_status_register = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !read_status_register_reg && !wb_we_i && (wb_adr_i[3:0] == 4'h4) ;
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wire read_status_register = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !read_status_register_reg && !wb_we_i && (wb_adr_i[3:0] == 4'h4) ;
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reg send_command_reg ;
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reg send_command_reg ;
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wire send_command = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !send_command_reg && wb_we_i && (wb_adr_i[3:0] == 4'h4) ;
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wire send_command = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !send_command_reg && wb_we_i && (wb_adr_i[3:0] == 4'h4) ;
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reg write_devide_reg ;
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reg write_devide_reg0 ;
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wire write_devide = wb_cyc_i && wb_stb_i && wb_sel_i[3] && wb_sel_i[2] && !wb_ack_o && !write_devide_reg && wb_we_i && (wb_adr_i[3:0] == 4'h8) ;
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wire write_devide0 = wb_cyc_i && wb_stb_i && wb_sel_i[2] && !wb_ack_o && !write_devide_reg0 && wb_we_i && (wb_adr_i[3:0] == 4'h8) ;
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reg read_devide_reg ;
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wire read_devide = wb_cyc_i && wb_stb_i && wb_sel_i[3] && wb_sel_i[2] && !wb_ack_o && !read_devide_reg && !wb_we_i && (wb_adr_i[3:0] == 4'h8) ;
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//reg read_devide_reg ;
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wire read_devide = wb_cyc_i && wb_stb_i && ( wb_sel_i[2]|| wb_sel_i [3] ) && !wb_we_i && (wb_adr_i[3:0] == 4'h8) ;
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reg write_devide_reg1 ;
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wire write_devide1 = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !write_devide_reg1 && wb_we_i && (wb_adr_i[3:0] == 4'h8) ;
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reg translate_o,
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reg translate_o,
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enable1,
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enable1,
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system,
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system,
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interrupt1 ;
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interrupt1 ;
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Line 268... |
begin
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begin
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send_command_reg <= #1 1'b0 ;
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send_command_reg <= #1 1'b0 ;
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read_input_buffer_reg <= #1 1'b0 ;
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read_input_buffer_reg <= #1 1'b0 ;
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write_output_buffer_reg <= #1 1'b0 ;
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write_output_buffer_reg <= #1 1'b0 ;
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read_status_register_reg <= #1 1'b0 ;
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read_status_register_reg <= #1 1'b0 ;
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write_devide_reg <= #1 1'b0 ;
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write_devide_reg0 <= #1 1'b0 ;
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read_devide_reg <= #1 1'b0 ;
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//read_devide_reg <= #1 1'b0 ;
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write_devide_reg1 <= #1 1'b0 ;
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end
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end
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else
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else
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begin
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begin
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send_command_reg <= #1 send_command ;
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send_command_reg <= #1 send_command ;
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read_input_buffer_reg <= #1 read_input_buffer ;
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read_input_buffer_reg <= #1 read_input_buffer ;
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write_output_buffer_reg <= #1 write_output_buffer ;
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write_output_buffer_reg <= #1 write_output_buffer ;
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read_status_register_reg <= #1 read_status_register ;
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read_status_register_reg <= #1 read_status_register ;
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write_devide_reg <= #1 write_devide ;
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write_devide_reg0 <= #1 write_devide0 ;
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read_devide_reg <= #1 read_devide ;
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//read_devide_reg <= #1 read_devide ;
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write_devide_reg1 <= #1 write_devide1 ;
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end
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end
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end
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end
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always@(posedge wb_clk_i or posedge wb_rst_i)
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always@(posedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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| Line 464... |
Line 474... |
else
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else
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wb_ack_o <= #1 cyc_i_previous && stb_i_previous ;
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wb_ack_o <= #1 cyc_i_previous && stb_i_previous ;
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end
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end
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reg [31:0] wb_dat_o ;
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reg [31:0] wb_dat_o ;
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wire wb_read = read_input_buffer_reg || read_status_register_reg ;
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wire wb_read = read_input_buffer_reg || read_status_register_reg || read_devide ;
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wire [15:0] output_data = read_status_register_reg ? {2{status_byte}} : read_devide_reg ? devide_reg : {2{input_buffer}} ;
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wire [15:0] output_data = read_status_register_reg ? {2{status_byte}} : read_devide ? devide_reg : {2{input_buffer}} ;
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always@(posedge wb_clk_i or posedge wb_rst_i)
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always@(posedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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if ( wb_rst_i )
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if ( wb_rst_i )
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wb_dat_o <= #1 32'h0 ;
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wb_dat_o <= #1 32'h0 ;
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else if ( wb_read )
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else if ( wb_read )
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| Line 509... |
Line 519... |
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always@(posedge wb_clk_i or posedge wb_rst_i)
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always@(posedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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if ( wb_rst_i )
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if ( wb_rst_i )
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devide_reg <= #1 8'h00 ;
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devide_reg <= #1 8'h00 ;
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else if ( write_devide_reg )
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else
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devide_reg <= #1 wb_dat_i_sampled ;
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begin
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if ( write_devide_reg0 )
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devide_reg[7:0] <= #1 wb_dat_i_sampled[7:0] ;
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if ( write_devide_reg1 )
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devide_reg[15:8] <= #1 wb_dat_i_sampled[15:8] ;
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end
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end
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end
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always@(posedge wb_clk_i or posedge wb_rst_i)
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always@(posedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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if ( wb_rst_i )
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if ( wb_rst_i )
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