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[/] [ps2/] [tags/] [rel_2/] [rtl/] [verilog/] [ps2_translation_table.v] - Diff between revs 2 and 13
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2002/02/18 16:16:56 mihad
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// Initial project import - working
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//
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//
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//
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`include "ps2_defines.v"
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`include "ps2_defines.v"
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// synopsys translate_off
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// synopsys translate_off
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data_o,
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data_o,
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rx_data_ready_i,
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rx_data_ready_i,
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rx_translated_data_ready_o,
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rx_translated_data_ready_o,
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rx_read_i,
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rx_read_i,
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rx_read_o,
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rx_read_o,
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rx_extended_i,
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rx_released_i
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rx_released_i
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) ;
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) ;
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input reset_i,
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input reset_i,
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clock_i,
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clock_i,
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rx_read_i ;
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rx_read_i ;
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output rx_translated_data_ready_o ;
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output rx_translated_data_ready_o ;
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output rx_read_o ;
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output rx_read_o ;
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input rx_extended_i,
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input rx_released_i ;
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rx_released_i ;
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wire translation_table_write_enable = we_i && (!translate_i || !rx_data_ready_i) ;
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wire translation_table_write_enable = we_i && (!translate_i || !rx_data_ready_i) ;
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wire [7:0] translation_table_address = ((we_i || re_i) && (!rx_data_ready_i || !translate_i)) ? address_i : code_i ;
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wire [7:0] translation_table_address = ((we_i || re_i) && (!rx_data_ready_i || !translate_i)) ? address_i : code_i ;
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wire translation_table_enable = we_i || re_i || (translate_i && rx_data_ready_i) ;
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wire translation_table_enable = we_i || re_i || (translate_i && rx_data_ready_i) ;
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