| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2003/05/28 16:26:51 simons
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// Change the address width.
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//
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// Revision 1.5 2002/04/09 13:17:03 mihad
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// Revision 1.5 2002/04/09 13:17:03 mihad
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// Mouse interface testcases added
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// Mouse interface testcases added
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//
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//
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// Revision 1.4 2002/02/20 16:35:34 mihad
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// Revision 1.4 2002/02/20 16:35:34 mihad
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// Little/big endian changes continued
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// Little/big endian changes continued
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| Line 161... |
Line 164... |
`endif
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`endif
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reg ok ;
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reg ok ;
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reg error ;
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reg error ;
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reg ok_o;
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integer rem;
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integer wb_period;
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reg wb_rem;
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reg [15:0] wb_dev_data;
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integer watchdog_timer ;
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integer watchdog_timer ;
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reg watchdog_reset ;
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reg watchdog_reset ;
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reg watchdog_reset_previous ;
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reg watchdog_reset_previous ;
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reg [7:0] normal_scancode_set2_mem [0:`PS2_NUM_OF_NORMAL_SCANCODES - 1] ;
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reg [7:0] normal_scancode_set2_mem [0:`PS2_NUM_OF_NORMAL_SCANCODES - 1] ;
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| Line 174... |
Line 185... |
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`define WB_PERIOD (1/`WB_FREQ)
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`define WB_PERIOD (1/`WB_FREQ)
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initial
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initial
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begin
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begin
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$readmemh("../../../bench/data/normal_scancodes_set2.hex", normal_scancode_set2_mem) ;
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$readmemh("../../../bench/data/normal_scancodes_set2.hex", normal_scancode_set2_mem) ;
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$readmemh("../../../bench/data/normal_scancodes_set1.hex", normal_scancode_set1_mem) ;
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$readmemh("../../../bench/data/normal_scancodes_set1.hex", normal_scancode_set1_mem) ;
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$readmemh("../../../bench/data/extended_scancodes_set2.hex", extended_scancode_set2_mem) ;
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$readmemh("../../../bench/data/extended_scancodes_set2.hex", extended_scancode_set2_mem) ;
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$readmemh("../../../bench/data/extended_scancodes_set1.hex", extended_scancode_set1_mem) ;
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$readmemh("../../../bench/data/extended_scancodes_set1.hex", extended_scancode_set1_mem) ;
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if ( ((`PS2_TIMER_5USEC_VALUE_PP * `WB_PERIOD) < 5000) || ((`PS2_TIMER_5USEC_VALUE_PP * `WB_PERIOD) > 6000) )
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begin
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$display("Warning! 5us timer max value is not defined correctly regarding to WISHBONE bus clock!") ;
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$stop ;
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end
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if ( ((`PS2_TIMER_60USEC_VALUE_PP * `WB_PERIOD) < 60000) || ((`PS2_TIMER_60USEC_VALUE_PP * `WB_PERIOD) > 61000) )
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begin
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$display("Warning! 60us timer max value is not defined correctly regarding to WISHBONE bus clock!") ;
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$stop ;
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end
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if ( (1 << `PS2_TIMER_5USEC_BITS_PP) < `PS2_TIMER_5USEC_VALUE_PP )
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begin
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$display("Warning! 5us timer max value is not defined correctly regarding to the length in bits of 5us timer!") ;
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$stop ;
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end
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if ( (1 << `PS2_TIMER_60USEC_BITS_PP) < `PS2_TIMER_60USEC_VALUE_PP )
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wb_period =50;
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begin
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wb_rem = 1'b0;
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$display("Warning! 60us timer max value is not defined correctly regarding to the length in bits of 60us timer!") ;
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rem =0;
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$stop ;
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end
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watchdog_timer = 32'h1000_0000 ;
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watchdog_timer = 32'h1000_0000 ;
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watchdog_reset = 0 ;
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watchdog_reset = 0 ;
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watchdog_reset_previous = 0 ;
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watchdog_reset_previous = 0 ;
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| Line 214... |
Line 207... |
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#100 ;
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#100 ;
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repeat ( 10 )
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repeat ( 10 )
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@(posedge wb_clock) ;
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@(posedge wb_clock) ;
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wb_reset <= 1'b0 ;
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wb_reset <= 1'b0 ;
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repeat(6)
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begin
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@(posedge wb_clock)
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begin
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rem = 5000 % wb_period;
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if (rem > 0)
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begin
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wb_rem = 1'b1;
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end
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else
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begin
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wb_rem = 1'b0;
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end
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end
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begin
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devider_write(4'h8,5000/wb_period + wb_rem ,ok_o);
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@(posedge wb_clock) ;
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@(posedge wb_clock) ;
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#1 initialize_controler ;
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#1 initialize_controler ;
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test_scan_code_receiving ;
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test_scan_code_receiving ;
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| Line 241... |
Line 258... |
end
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end
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join
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join
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`endif
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`endif
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test_keyboard_inhibit ;
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test_keyboard_inhibit ;
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wb_period = wb_period + 10 ;
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end
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end
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$display("end simulation");
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#400 $stop ;
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#400 $stop ;
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end
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end
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always
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always
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#(`WB_PERIOD / 2) wb_clock = !wb_clock ;
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#(wb_period/2.0) wb_clock = !wb_clock ;
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wire wb_cyc,
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wire wb_cyc,
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wb_stb,
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wb_stb,
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wb_we,
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wb_we,
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wb_ack,
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wb_ack,
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| Line 268... |
Line 289... |
.wb_rst_i (wb_reset),
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.wb_rst_i (wb_reset),
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.wb_cyc_i (wb_cyc),
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.wb_cyc_i (wb_cyc),
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.wb_stb_i (wb_stb),
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.wb_stb_i (wb_stb),
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.wb_we_i (wb_we),
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.wb_we_i (wb_we),
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.wb_sel_i (wb_sel),
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.wb_sel_i (wb_sel),
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.wb_adr_i (wb_adr[2:0]),
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.wb_adr_i (wb_adr[3:0]),
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.wb_dat_i (wb_dat_m_s),
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.wb_dat_i (wb_dat_m_s),
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.wb_dat_o (wb_dat_s_m),
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.wb_dat_o (wb_dat_s_m),
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.wb_ack_o (wb_ack),
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.wb_ack_o (wb_ack),
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.wb_int_o (wb_int),
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.wb_int_o (wb_int),
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| Line 874... |
Line 895... |
ok_o = 0 ;
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ok_o = 0 ;
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end
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end
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end
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end
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endtask // kbd_write
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endtask // kbd_write
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task devider_write ;
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input [31:0] address_i ;
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input [31:16] data_i ;
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output ok_o ;
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reg `WRITE_STIM_TYPE write_data ;
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reg `WRITE_RETURN_TYPE write_status ;
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reg `WB_TRANSFER_FLAGS flags ;
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begin:main
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ok_o = 1 ;
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flags`WB_TRANSFER_SIZE = 1 ;
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flags`WB_TRANSFER_AUTO_RTY = 0 ;
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flags`WB_TRANSFER_CAB = 0 ;
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flags`INIT_WAITS = 0 ;
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flags`SUBSEQ_WAITS = 0 ;
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write_data`WRITE_ADDRESS = address_i ;
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write_data`WRITE_DATA = {2{data_i}};
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write_data`WRITE_SEL = 4'hC ;
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i_wb_master.wb_single_write( write_data, flags, write_status ) ;
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if ( write_status`CYC_ACK !== 1 )
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begin
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$display("Error! Keyboard controller didn't acknowledge single write access") ;
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#400 $stop ;
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ok_o = 0 ;
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end
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end
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endtask // devider_write
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task test_scan_code_receiving ;
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task test_scan_code_receiving ;
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reg ok_keyboard ;
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reg ok_keyboard ;
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reg ok_controler ;
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reg ok_controler ;
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reg ok ;
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reg ok ;
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reg [7:0] data ;
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reg [7:0] data ;
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| Line 1232... |
Line 1284... |
reg ok_keyboard ;
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reg ok_keyboard ;
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reg error ;
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reg error ;
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reg [7:0] data ;
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reg [7:0] data ;
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begin:main
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begin:main
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// first test, if keyboard stays inhibited after character is received, but not read from the controler
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// first test, if keyboard stays inhibited after character is received, but not read from the controler
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i_ps2_keyboard_model.kbd_send_char
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i_ps2_keyboard_model.kbd_send_char
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(
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(
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8'hE0,
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8'hE0,
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ok_keyboard,
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ok_keyboard,
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error
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error
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| Line 1252... |
Line 1305... |
$display("Something is wrong! Keyboard wasn't able to send a character!") ;
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$display("Something is wrong! Keyboard wasn't able to send a character!") ;
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#1 disable main ;
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#1 disable main ;
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end
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end
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// wait 5 us to see, if keyboard is inhibited
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// wait 5 us to see, if keyboard is inhibited
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#5000 ;
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#60000 ;
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// now check, if clock line is low!
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// now check, if clock line is low!
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if ( kbd_clk_cable !== 0 )
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if ( kbd_clk_cable !== 0 )
|
begin
|
begin
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$display("Error! Keyboard wasn't inhibited when output buffer was filled!") ;
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$display("Error! Keyboard wasn't inhibited when output buffer was filled!") ;
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