| Line 129... |
Line 129... |
rx_read, // rx_read_ack_i
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rx_read, // rx_read_ack_i
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tx_data,
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tx_data,
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tx_write,
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tx_write,
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tx_write_ack_o,
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tx_write_ack_o,
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tx_error_no_keyboard_ack,
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tx_error_no_keyboard_ack,
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translate
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translate,
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devide_reg_i
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);
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);
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// Parameters
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// Parameters
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|
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// The timer value can be up to (2^bits) inclusive.
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// The timer value can be up to (2^bits) inclusive.
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parameter TIMER_60USEC_VALUE_PP = 2950; // Number of sys_clks for 60usec.
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parameter TIMER_60USEC_VALUE_PP = 2950; // Number of sys_clks for 60usec.
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parameter TIMER_60USEC_BITS_PP = 12; // Number of bits needed for timer
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parameter TIMER_60USEC_BITS_PP = 12; // Number of bits needed for timer
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parameter TIMER_5USEC_VALUE_PP = 186; // Number of sys_clks for debounce
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parameter TIMER_5USEC_VALUE_PP = 186; // Number of sys_clks for debounce
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parameter TIMER_5USEC_BITS_PP = 8; // Number of bits needed for timer
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parameter TIMER_5USEC_BITS_PP = 8; // Number of bits needed for timer
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| Line 189... |
Line 191... |
input tx_write;
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input tx_write;
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output tx_write_ack_o;
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output tx_write_ack_o;
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output tx_error_no_keyboard_ack;
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output tx_error_no_keyboard_ack;
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input translate ;
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input translate ;
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input [15:0] devide_reg_i;
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reg rx_released;
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reg rx_released;
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reg [7:0] rx_scan_code;
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reg [7:0] rx_scan_code;
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reg rx_data_ready;
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reg rx_data_ready;
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reg tx_error_no_keyboard_ack;
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reg tx_error_no_keyboard_ack;
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| Line 228... |
Line 232... |
reg hold_released; // Holds prior value, cleared at rx_output_strobe
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reg hold_released; // Holds prior value, cleared at rx_output_strobe
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reg ps2_clk_s; // Synchronous version of this input
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reg ps2_clk_s; // Synchronous version of this input
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reg ps2_data_s; // Synchronous version of this input
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reg ps2_data_s; // Synchronous version of this input
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reg ps2_clk_hi_z; // Without keyboard, high Z equals 1 due to pullups.
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reg ps2_clk_hi_z; // Without keyboard, high Z equals 1 due to pullups.
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reg ps2_data_hi_z; // Without keyboard, high Z equals 1 due to pullups.
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reg ps2_data_hi_z; // Without keyboard, high Z equals 1 due to pullups.
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reg ps2_clk_ms;
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reg ps2_data_ms;
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reg [15:0] timer_5usec;
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reg timer_done;
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//--------------------------------------------------------------------------
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//--------------------------------------------------------------------------
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// Module code
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// Module code
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|
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assign ps2_clk_en_o_ = ps2_clk_hi_z ;
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assign ps2_clk_en_o_ = ps2_clk_hi_z ;
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| Line 240... |
Line 252... |
// Input "synchronizing" logic -- synchronizes the inputs to the state
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// Input "synchronizing" logic -- synchronizes the inputs to the state
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// machine clock, thus avoiding errors related to
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// machine clock, thus avoiding errors related to
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// spurious state machine transitions.
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// spurious state machine transitions.
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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ps2_clk_s <= ps2_clk_i;
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ps2_clk_ms <= ps2_clk_i;
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ps2_data_s <= ps2_data_i;
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ps2_data_ms <= ps2_data_i;
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|
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ps2_clk_s <= ps2_clk_ms;
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ps2_data_s <= ps2_data_ms;
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|
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end
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end
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// State register
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// State register
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always @(posedge clk)
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always @(posedge clk or posedge reset)
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begin : m1_state_register
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begin : m1_state_register
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if (reset) m1_state <= m1_rx_clk_h;
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if (reset) m1_state <= m1_rx_clk_h;
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else m1_state <= m1_next_state;
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else m1_state <= m1_next_state;
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end
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end
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| Line 395... |
Line 411... |
default : m1_next_state <= m1_rx_clk_h;
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default : m1_next_state <= m1_rx_clk_h;
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endcase
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endcase
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end
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end
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// State register
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// State register
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always @(posedge clk)
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always @(posedge clk or posedge reset)
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begin : m2_state_register
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begin : m2_state_register
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if (reset) m2_state <= m2_rx_data_ready_ack;
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if (reset) m2_state <= m2_rx_data_ready_ack;
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else m2_state <= m2_next_state;
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else m2_state <= m2_next_state;
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end
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end
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|
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| Line 422... |
Line 438... |
default : m2_next_state <= m2_rx_data_ready_ack;
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default : m2_next_state <= m2_rx_data_ready_ack;
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endcase
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endcase
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end
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end
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|
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// This is the bit counter
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// This is the bit counter
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always @(posedge clk)
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always @(posedge clk or posedge reset)
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begin
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begin
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if ( reset
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if ( reset) bit_count <= 0;
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|| rx_shifting_done
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else if ( rx_shifting_done || (m1_state == m1_tx_wait_keyboard_ack) // After tx is done.
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|| (m1_state == m1_tx_wait_keyboard_ack) // After tx is done.
|
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) bit_count <= 0; // normal reset
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) bit_count <= 0; // normal reset
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else if (timer_60usec_done
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else if (timer_60usec_done
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&& (m1_state == m1_rx_clk_h)
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&& (m1_state == m1_rx_clk_h)
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&& (ps2_clk_s)
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&& (ps2_clk_s)
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) bit_count <= 0; // rx watchdog timer reset
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) bit_count <= 0; // rx watchdog timer reset
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| Line 451... |
Line 466... |
|
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// This is the ODD parity bit for the transmitted word.
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// This is the ODD parity bit for the transmitted word.
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assign tx_parity_bit = ~^tx_data;
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assign tx_parity_bit = ~^tx_data;
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|
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// This is the shift register
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// This is the shift register
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always @(posedge clk)
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always @(posedge clk or posedge reset)
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begin
|
begin
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if (reset) q <= 0;
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if (reset) q <= 0;
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else if (tx_write_ack_o) q <= {1'b1,tx_parity_bit,tx_data,1'b0};
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else if (tx_write_ack_o) q <= {1'b1,tx_parity_bit,tx_data,1'b0};
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else if ( (m1_state == m1_rx_falling_edge_marker)
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else if ( (m1_state == m1_rx_falling_edge_marker)
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||(m1_state == m1_tx_rising_edge_marker) )
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||(m1_state == m1_tx_rising_edge_marker) )
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| Line 464... |
Line 479... |
|
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// This is the 60usec timer counter
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// This is the 60usec timer counter
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always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
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if (~enable_timer_60usec) timer_60usec_count <= 0;
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if (~enable_timer_60usec) timer_60usec_count <= 0;
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else if (~timer_60usec_done) timer_60usec_count <= timer_60usec_count + 1;
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else if ( timer_done && !timer_60usec_done)
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timer_60usec_count<= timer_60usec_count +1;
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end
|
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assign timer_60usec_done = (timer_60usec_count == (TIMER_60USEC_VALUE_PP ));
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|
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|
|
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always @(posedge clk or posedge reset)
|
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if (reset) timer_5usec <= 1;
|
|
else if (!enable_timer_60usec) timer_5usec <= 1;
|
|
else if (timer_5usec == devide_reg_i)
|
|
begin
|
|
timer_5usec <= 1;
|
|
timer_done <= 1;
|
|
end
|
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else
|
|
begin
|
|
timer_5usec<= timer_5usec +1;
|
|
timer_done <= 0;
|
end
|
end
|
assign timer_60usec_done = (timer_60usec_count == (TIMER_60USEC_VALUE_PP - 1));
|
|
|
|
// This is the 5usec timer counter
|
// This is the 5usec timer counter
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
if (~enable_timer_5usec) timer_5usec_count <= 0;
|
if (~enable_timer_5usec) timer_5usec_count <= 0;
|
else if (~timer_5usec_done) timer_5usec_count <= timer_5usec_count + 1;
|
else if (~timer_5usec_done) timer_5usec_count <= timer_5usec_count + 1;
|
end
|
end
|
assign timer_5usec_done = (timer_5usec_count == TIMER_5USEC_VALUE_PP - 1);
|
assign timer_5usec_done = (timer_5usec_count == devide_reg_i -1);
|
|
|
|
|
// Create the signals which indicate special scan codes received.
|
// Create the signals which indicate special scan codes received.
|
// These are the "unlatched versions."
|
// These are the "unlatched versions."
|
assign released = (q[8:1] == `RELEASE_CODE) && rx_shifting_done && translate ;
|
assign released = (q[8:1] == `RELEASE_CODE) && rx_shifting_done && translate ;
|
|
|
// Store the special scan code status bits
|
// Store the special scan code status bits
|
// Not the final output, but an intermediate storage place,
|
// Not the final output, but an intermediate storage place,
|
// until the entire set of output data can be assembled.
|
// until the entire set of output data can be assembled.
|
always @(posedge clk)
|
always @(posedge clk or posedge reset)
|
begin
|
begin
|
if (reset || rx_output_event)
|
if (reset) hold_released <= 0;
|
|
else if (rx_output_event)
|
begin
|
begin
|
hold_released <= 0;
|
hold_released <= 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (rx_shifting_done && released) hold_released <= 1;
|
if (rx_shifting_done && released) hold_released <= 1;
|
end
|
end
|
end
|
end
|
|
|
// Output the special scan code flags, the scan code and the ascii
|
// Output the special scan code flags, the scan code and the ascii
|
always @(posedge clk)
|
always @(posedge clk or posedge reset)
|
begin
|
begin
|
if (reset)
|
if (reset)
|
begin
|
begin
|
rx_released <= 0;
|
rx_released <= 0;
|
rx_scan_code <= 0;
|
rx_scan_code <= 0;
|
