Subversion Repositories ps2

// synopsys translate_off

// synopsys translate_off

`resetall

`resetall

`include "timescale.v"

`include "timescale.v"

// synopsys translate_on

// synopsys translate_on

`define TOTAL_BITS   11

`define TOTAL_BITS   11

`define RELEASE_CODE 16'hF0

`define RELEASE_CODE 16'hF0

module ps2_keyboard (

module ps2_keyboard (

  clk,

  clk,

  reset,

  reset,

  ps2_clk_en_o_,

  ps2_clk_en_o_,

  ps2_data_en_o_,

  ps2_data_en_o_,

  ps2_clk_i,

  ps2_clk_i,

  ps2_data_i,

  ps2_data_i,

  rx_released,

  rx_released,

  rx_scan_code,

  rx_scan_code,

  rx_data_ready,       // rx_read_o

  rx_data_ready,       // rx_read_o

  rx_read,             // rx_read_ack_i

  rx_read,             // rx_read_ack_i

  tx_data,

  tx_data,

  tx_write,

  tx_write,

  tx_write_ack_o,

  tx_write_ack_o,

// The timer value can be up to (2^bits) inclusive.

// The timer value can be up to (2^bits) inclusive.

parameter TIMER_60USEC_VALUE_PP = 2950; // Number of sys_clks for 60usec.

parameter TIMER_60USEC_VALUE_PP = 2950; // Number of sys_clks for 60usec.

parameter TIMER_60USEC_BITS_PP  = 12;   // Number of bits needed for timer

parameter TIMER_60USEC_BITS_PP  = 12;   // Number of bits needed for timer

parameter TIMER_5USEC_VALUE_PP = 186;   // Number of sys_clks for debounce

parameter TIMER_5USEC_VALUE_PP = 186;   // Number of sys_clks for debounce

parameter TIMER_5USEC_BITS_PP  = 8;     // Number of bits needed for timer

parameter TIMER_5USEC_BITS_PP  = 8;     // Number of bits needed for timer

// State encodings, provided as parameters

// State encodings, provided as parameters

// for flexibility to the one instantiating the module.

// for flexibility to the one instantiating the module.

// In general, the default values need not be changed.

// In general, the default values need not be changed.

input reset;

input reset;

output ps2_clk_en_o_ ;

output ps2_clk_en_o_ ;

output ps2_data_en_o_ ;

output ps2_data_en_o_ ;

input  ps2_clk_i ;

input  ps2_clk_i ;

input  ps2_data_i ;

input  ps2_data_i ;

output rx_released;

output rx_released;

output [7:0] rx_scan_code;

output [7:0] rx_scan_code;

output rx_data_ready;

output rx_data_ready;

input rx_read;

input rx_read;

input [7:0] tx_data;

input [7:0] tx_data;

input tx_write;

input tx_write;

output tx_write_ack_o;

output tx_write_ack_o;

output tx_error_no_keyboard_ack;

output tx_error_no_keyboard_ack;

input  translate ;

input  translate ;

reg rx_released;

reg rx_released;

reg [7:0] rx_scan_code;

reg [7:0] rx_scan_code;

reg rx_data_ready;

reg rx_data_ready;

reg tx_error_no_keyboard_ack;

reg tx_error_no_keyboard_ack;

// Internal signal declarations

// Internal signal declarations

wire timer_60usec_done;

wire timer_60usec_done;

wire timer_5usec_done;

wire timer_5usec_done;

wire released;

wire released;

                         // NOTE: These two signals used to be one.  They

                         // NOTE: These two signals used to be one.  They

                         //       were split into two signals because of

                         //       were split into two signals because of

                         //       shift key trapping.  With shift key

                         //       shift key trapping.  With shift key

                         //       trapping, no event is generated externally,

                         //       trapping, no event is generated externally,

wire rx_output_strobe;   // Used to produce the actual output.

wire rx_output_strobe;   // Used to produce the actual output.

wire tx_parity_bit;

wire tx_parity_bit;

wire rx_shifting_done;

wire rx_shifting_done;

wire tx_shifting_done;

wire tx_shifting_done;

reg [`TOTAL_BITS-1:0] q;

reg [`TOTAL_BITS-1:0] q;

reg [3:0] m1_state;

reg [3:0] m1_state;

reg [3:0] m1_next_state;

reg [3:0] m1_next_state;

reg m2_state;

reg m2_state;

reg [3:0] bit_count;

reg [3:0] bit_count;

reg enable_timer_60usec;

reg enable_timer_60usec;

reg enable_timer_5usec;

reg enable_timer_5usec;

reg [TIMER_60USEC_BITS_PP-1:0] timer_60usec_count;

reg [TIMER_60USEC_BITS_PP-1:0] timer_60usec_count;

reg [TIMER_5USEC_BITS_PP-1:0] timer_5usec_count;

reg [TIMER_5USEC_BITS_PP-1:0] timer_5usec_count;

reg hold_released;    // Holds prior value, cleared at rx_output_strobe

reg hold_released;    // Holds prior value, cleared at rx_output_strobe

reg ps2_clk_s;        // Synchronous version of this input

reg ps2_clk_s;        // Synchronous version of this input

reg ps2_data_s;       // Synchronous version of this input

reg ps2_data_s;       // Synchronous version of this input

reg ps2_clk_hi_z;     // Without keyboard, high Z equals 1 due to pullups.

reg ps2_clk_hi_z;     // Without keyboard, high Z equals 1 due to pullups.

reg ps2_data_hi_z;    // Without keyboard, high Z equals 1 due to pullups.

reg ps2_data_hi_z;    // Without keyboard, high Z equals 1 due to pullups.

assign timer_5usec_done = (timer_5usec_count == TIMER_5USEC_VALUE_PP - 1);

assign timer_5usec_done = (timer_5usec_count == TIMER_5USEC_VALUE_PP - 1);

// Create the signals which indicate special scan codes received.

// Create the signals which indicate special scan codes received.

// These are the "unlatched versions."

// These are the "unlatched versions."

assign released = (q[8:1] == `RELEASE_CODE) && rx_shifting_done && translate ;

assign released = (q[8:1] == `RELEASE_CODE) && rx_shifting_done && translate ;

// Store the special scan code status bits

// Store the special scan code status bits

// Not the final output, but an intermediate storage place,

// Not the final output, but an intermediate storage place,

// until the entire set of output data can be assembled.

// until the entire set of output data can be assembled.

always @(posedge clk)

always @(posedge clk)

begin

begin

  if (reset || rx_output_event)

  if (reset || rx_output_event)

  begin

  begin

    hold_released <= 0;

    hold_released <= 0;

  end

  end

  else

  else

  begin

  begin

    if (rx_shifting_done && released) hold_released <= 1;

    if (rx_shifting_done && released) hold_released <= 1;

  end

  end

end

end

// Output the special scan code flags, the scan code and the ascii

// Output the special scan code flags, the scan code and the ascii

always @(posedge clk)

always @(posedge clk)

begin

begin

  if (reset)

  if (reset)

  begin

  begin

    rx_released <= 0;

    rx_released <= 0;

    rx_scan_code <= 0;

    rx_scan_code <= 0;

  end

  end

  else if (rx_output_strobe)

  else if (rx_output_strobe)

  begin

  begin

    rx_released <= hold_released;

    rx_released <= hold_released;

    rx_scan_code <= q[8:1];

    rx_scan_code <= q[8:1];

  end

  end

end

end

// Store the final rx output data only when all extend and release codes

// Store the final rx output data only when all extend and release codes

// are received and the next (actual key) scan code is also ready.

// are received and the next (actual key) scan code is also ready.

// (the presence of rx_extended or rx_released refers to the

// (the presence of rx_extended or rx_released refers to the

// the current latest scan code received, not the previously latched flags.)

// the current latest scan code received, not the previously latched flags.)

assign rx_output_event  = (rx_shifting_done

assign rx_output_event  = (rx_shifting_done

                          && ~released

                          && ~released

                          );

                          );

assign rx_output_strobe = (rx_shifting_done

assign rx_output_strobe = (rx_shifting_done

                          && ~released

                          && ~released

                          );

                          );

endmodule

endmodule

//`undefine TOTAL_BITS

//`undefine TOTAL_BITS

//`undefine EXTEND_CODE

//`undefine EXTEND_CODE

//`undefine RELEASE_CODE

//`undefine RELEASE_CODE