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Line 42... |
module ps2_host_rx(
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module ps2_host_rx(
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input wire sys_clk,
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input wire sys_clk,
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input wire sys_rst,
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input wire sys_rst,
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input wire ps2_clk_negedge,
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input wire ps2_clk_negedge,
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input wire ps2_data,
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input wire ps2_data,
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output wire [7:0] rx_data,
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output reg [7:0] rx_data,
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output wire ready,
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output reg ready,
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output wire error
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output reg error
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);
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);
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// Read in 11 bit long frame. 12th bit marks end of frame.
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// Read in 11 bit long frame.
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reg [11:0] frame;
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reg [11:0] frame;
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always @(posedge sys_clk)
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always @(posedge sys_clk)
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begin
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begin
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if (sys_rst | ready) begin
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if (sys_rst | ready) begin
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frame <= 1;
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frame <= 1;
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| Line 59... |
Line 59... |
else begin
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else begin
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frame <= (ps2_clk_negedge) ? {frame[10:0], ps2_data} : frame;
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frame <= (ps2_clk_negedge) ? {frame[10:0], ps2_data} : frame;
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end
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end
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end
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end
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// Return rx_data in most significant bit first order.
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assign rx_data = {frame[2], frame[3], frame[4], frame[5],
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frame[6], frame[7], frame[8], frame[9]};
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// 12th bit marks end of frame.
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// 12th bit marks end of frame.
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assign ready = frame[11];
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always @(posedge sys_clk)
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begin
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ready <= (sys_rst) ? 0 : frame[11];
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end
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// Return rx_data in most significant bit first order.
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always @(posedge sys_clk)
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begin
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if (sys_rst) begin
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rx_data <= 0;
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end
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else begin
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rx_data <= (frame[11]) ? {frame[2], frame[3], frame[4], frame[5],
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frame[6], frame[7], frame[8], frame[9]} : rx_data;
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end
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end
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// Check that 1st bit is 0, odd parity bit is correct and last bit is 1.
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// Check that 1st bit is 0, odd parity bit is correct and last bit is 1.
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assign error = ~(~frame[10] & (~frame[1] == ^frame[9:2]) & frame[0]);
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always @(posedge sys_clk)
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begin
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if (sys_rst) begin
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error <= 0;
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end
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else begin
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error <= (frame[11]) ? ~(~frame[10] & (~frame[1] == ^frame[9:2]) & frame[0]) : error;
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end
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end
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endmodule
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endmodule
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