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[/] [pss/] [trunk/] [pss/] [hdl/] [pss/] [pss.v] - Diff between revs 2 and 5

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Rev 2	Rev 5
Line 2...	Line 2...
`PSS`	`PSS`

`Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>`	`Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>`
`All rights reserved.`	`All rights reserved.`

`Version 0.9`	`Version 0.99`

`The FreeBSD license`	`The FreeBSD license`

`Redistribution and use in source and binary forms, with or without`	`Redistribution and use in source and binary forms, with or without`
`modification, are permitted provided that the following conditions`	`modification, are permitted provided that the following conditions`
Line 36...	Line 36...

`module pss`	`module pss`
`#(`	`#(`
`parameter CPU_PRESENT = 1,`	`parameter CPU_PRESENT = 1,`
`parameter CPU_RESET_DEFAULT = 1,`	`parameter CPU_RESET_DEFAULT = 1,`
`parameter A31_DEFAULTS = 1,`	`parameter A31_DEFAULT = 1,`
`parameter MEM_SIZE_KB = 1,`	`parameter MEM_SIZE_KB = 1,`
`parameter MEM_DATA = ""`	`parameter MEM_DATA = ""`
`)`	`)`
`(`	`(`
`input clk_i, arst_i,`	`input clk_i,`
`output srst_o,`	`input arst_i, srst_i,`
	`output srst_o, ext_rst_o,`

`input rx_i,`	`input rx_i,`
`output tx_o,`	`output tx_o,`

`input [3:0] INT_i,`	`input [3:0] INT_bi,`

`// Expansion bus`	`// Expansion bus`
`output xport_req_o,`	`output xport_req_o,`
`input xport_ack_i,`	`input xport_ack_i,`
`input xport_err_i,`	`input xport_err_i,`
Line 60...	Line 61...
`output [31:0] xport_wdata_bo,`	`output [31:0] xport_wdata_bo,`
`input xport_resp_i,`	`input xport_resp_i,`
`input [31:0] xport_rdata_bi`	`input [31:0] xport_rdata_bi`
`);`	`);`

`wire sync_rst, udm_rst;`	`wire zpu_uc_srst, udm_rst;`
`as_reset_cntrl as_reset_cntrl`	`assign zpu_uc_srst = srst_i \| udm_rst;`
`(`
`.clk_i(clk_i),`
`.rst_i(arst_i),`
`.rst_o(sync_rst)`
`);`

`assign srst_o = sync_rst \| udm_rst;`

`wire dbg_bus_enb;`	`wire dbg_bus_enb;`
`wire dbg_bus_we;`	`wire dbg_bus_we;`
`wire [31:0] dbg_bus_addr;`	`wire [31:0] dbg_bus_addr;`
`wire [31:0] dbg_bus_wdata;`	`wire [31:0] dbg_bus_wdata;`
Line 80...	Line 74...
`wire dbg_bus_resp;`	`wire dbg_bus_resp;`

`udm udm`	`udm udm`
`(`	`(`
`.clk_i(clk_i),`	`.clk_i(clk_i),`
`.rst_i(sync_rst),`	`.rst_i(srst_o),`

`.rx_i(rx_i),`	`.rx_i(rx_i),`
`.tx_o(tx_o),`	`.tx_o(tx_o),`

`.rst_o(udm_rst),`	`.rst_o(udm_rst),`
Line 99...	Line 93...

`ZPU_uC`	`ZPU_uC`
`#(`	`#(`
`.CPU_PRESENT(CPU_PRESENT),`	`.CPU_PRESENT(CPU_PRESENT),`
`.CPU_RESET_DEFAULT(CPU_RESET_DEFAULT),`	`.CPU_RESET_DEFAULT(CPU_RESET_DEFAULT),`
`.A31_DEFAULTS(A31_DEFAULTS),`	`.A31_DEFAULT(A31_DEFAULT),`
`.MEM_DATA(MEM_DATA),`	`.MEM_DATA(MEM_DATA),`
`.MEM_SIZE_KB(MEM_SIZE_KB)`	`.MEM_SIZE_KB(MEM_SIZE_KB)`
`)`	`)`
`ZPU_uC`	`ZPU_uC`
`(`	`(`
`.clk_i(clk_i),`	`.clk_i(clk_i),`
`.rst_i(srst_o),`
`.INT_i(INT_i),`	`.arst_i(arst_i),`
	`.srst_o(srst_o),`

	`.srst_i(zpu_uc_srst),`
	`.ext_rst_o(ext_rst_o),`

	`.INT_bi(INT_bi),`

`// Expansion bus`	`// Expansion bus`
`.xport_req_o(xport_req_o),`	`.xport_req_o(xport_req_o),`
`.xport_ack_i(xport_ack_i),`	`.xport_ack_i(xport_ack_i),`
`.xport_err_i(xport_err_i),`	`.xport_err_i(xport_err_i),`

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[/] [pss/] [trunk/] [pss/] [hdl/] [pss/] [pss.v] - Diff between revs 2 and 5