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[/] [pss/] [trunk/] [pss/] [hdl/] [pss/] [zpu_uc/] [motherblock/] [pss_busbridge.v] - Diff between revs 5 and 7

Rev 5	Rev 7
Line 105...	Line 105...
`begin`	`begin`
`if (bus_we_i == 1'b1)`	`if (bus_we_i == 1'b1)`
`begin`	`begin`
`xport_req_o <= 1'b1;`	`xport_req_o <= 1'b1;`
`xport_we_o <= 1'b1;`	`xport_we_o <= 1'b1;`
`xport_addr_bo <= bus_addr_bi;`	`xport_addr_bo <= {a31_i, bus_addr_bi[30:0]};`
`xport_wdata_bo <= bus_wdata_bi;`	`xport_wdata_bo <= bus_wdata_bi;`
`xport_writemask_bo <= bus_writemask_bi;`	`xport_writemask_bo <= bus_writemask_bi;`
`bb_state <= ST_WR_WAIT_ACK;`	`bb_state <= ST_WR_WAIT_ACK;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`xport_req_o <= 1'b1;`	`xport_req_o <= 1'b1;`
`xport_we_o <= 1'b0;`	`xport_we_o <= 1'b0;`
`xport_addr_bo <= bus_addr_bi;`	`xport_addr_bo <= {a31_i, bus_addr_bi[30:0]};`
`xport_wdata_bo <= bus_wdata_bi;`	`xport_wdata_bo <= bus_wdata_bi;`
`xport_writemask_bo <= bus_writemask_bi;`	`xport_writemask_bo <= bus_writemask_bi;`
`bb_state <= ST_RD_WAIT_ACK;`	`bb_state <= ST_RD_WAIT_ACK;`
`end`	`end`
`end`	`end`