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module PSS_SFR
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module PSS_SFR
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#(
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#(
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parameter CPU_RESET_DEFAULT = 1,
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parameter CPU_RESET_DEFAULT = 1,
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parameter EXT_RESET_DEFAULT = 1,
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parameter A31_DEFAULT = 1,
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parameter A31_DEFAULT = 1,
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parameter MEM_SIZE_KB = 1
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parameter MEM_SIZE_KB = 1
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)
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)
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(
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(
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input clk_i, rst_i,
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input clk_i, rst_i,
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input trap_cpu_enb_i,
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input trap_cpu_enb_i,
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input [31:0] trap_cpu_addr_bi,
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input [31:0] trap_cpu_addr_bi,
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output reg cpu_reset_o,
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output reg cpu_reset_o,
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output reg ext_reset_o,
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output cpu_enb_o,
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output cpu_enb_o,
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output reg a31_o,
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output reg a31_o,
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input bus_error_i,
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input bus_error_i,
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input [31:0] bus_error_addr_bi,
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input [31:0] bus_error_addr_bi,
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begin
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begin
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if (rst_i)
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if (rst_i)
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begin
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begin
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cpu_reset_o <= CPU_RESET_DEFAULT;
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cpu_reset_o <= CPU_RESET_DEFAULT;
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ext_reset_o <= EXT_RESET_DEFAULT;
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a31_o <= A31_DEFAULT;
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a31_o <= A31_DEFAULT;
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trap_enable <= 1'b0;
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trap_enable <= 1'b0;
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trap_addr <= 32'h0;
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trap_addr <= 32'h0;
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if (bus_enb_i == 1'b1)
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if (bus_enb_i == 1'b1)
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begin
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begin
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if (bus_we_i == 1'b0)
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if (bus_we_i == 1'b0)
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case (bus_addr_bi[7:0])
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case (bus_addr_bi[7:0])
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REG_CPU_CONTROL_ADDR: bus_rdata_bo <= {cpu_present_i, 29'h0, cpu_break_i, cpu_reset_o};
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REG_CPU_CONTROL_ADDR: bus_rdata_bo <= {cpu_present_i, 28'h0, cpu_break_i, ext_reset_o, cpu_reset_o};
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REG_CPU_PC_ADDR: bus_rdata_bo <= cpu_pc_bi;
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REG_CPU_PC_ADDR: bus_rdata_bo <= cpu_pc_bi;
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REG_A31: bus_rdata_bo <= {31'h0, a31_o};
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REG_A31: bus_rdata_bo <= {31'h0, a31_o};
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REG_INTC_CONTROL_ADDR: bus_rdata_bo <= {31'h0, intc_ie_i};
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REG_INTC_CONTROL_ADDR: bus_rdata_bo <= {31'h0, intc_ie_i};
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REG_INTC_MASK_ADDR: bus_rdata_bo <= {24'h0, intc_mask_bo};
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REG_INTC_MASK_ADDR: bus_rdata_bo <= {24'h0, intc_mask_bo};
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REG_BUS_ERROR_ADDR_ADDR: bus_rdata_bo <= bus_error_addr;
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REG_BUS_ERROR_ADDR_ADDR: bus_rdata_bo <= bus_error_addr;
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REG_BUS_ERROR_PC_ADDR: bus_rdata_bo <= bus_error_pc;
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REG_BUS_ERROR_PC_ADDR: bus_rdata_bo <= bus_error_pc;
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endcase
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endcase
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else
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else
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case (bus_addr_bi[7:0])
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case (bus_addr_bi[7:0])
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REG_CPU_CONTROL_ADDR: cpu_reset_o <= bus_wdata_bi[0];
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REG_CPU_CONTROL_ADDR: begin cpu_reset_o <= bus_wdata_bi[0]; ext_reset_o <= bus_wdata_bi[1]; end
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REG_A31: a31_o <= bus_wdata_bi[0];
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REG_A31: a31_o <= bus_wdata_bi[0];
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REG_INTC_CONTROL_ADDR: begin intc_ie_we_o <= 1'b1; intc_ie_data_o <= bus_wdata_bi[0]; end
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REG_INTC_CONTROL_ADDR: begin intc_ie_we_o <= 1'b1; intc_ie_data_o <= bus_wdata_bi[0]; end
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REG_INTC_MASK_ADDR: intc_mask_bo <= bus_wdata_bi[7:0];
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REG_INTC_MASK_ADDR: intc_mask_bo <= bus_wdata_bi[7:0];
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REG_INTC_REQ_ADDR: begin intc_clr_cmd_o <= 1'b1; intc_clr_code_bo <= bus_wdata_bi[7:0]; end
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REG_INTC_REQ_ADDR: begin intc_clr_cmd_o <= 1'b1; intc_clr_code_bo <= bus_wdata_bi[7:0]; end
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