| Line 1... |
Line 1... |
module PSS_SFR
|
module PSS_SFR
|
#(
|
#(
|
parameter CPU_RESET_DEFAULT = 1,
|
parameter CPU_RESET_DEFAULT = 1,
|
|
parameter EXT_RESET_DEFAULT = 1,
|
parameter A31_DEFAULT = 1,
|
parameter A31_DEFAULT = 1,
|
parameter MEM_SIZE_KB = 1
|
parameter MEM_SIZE_KB = 1
|
)
|
)
|
(
|
(
|
input clk_i, rst_i,
|
input clk_i, rst_i,
|
| Line 23... |
Line 24... |
|
|
input trap_cpu_enb_i,
|
input trap_cpu_enb_i,
|
input [31:0] trap_cpu_addr_bi,
|
input [31:0] trap_cpu_addr_bi,
|
|
|
output reg cpu_reset_o,
|
output reg cpu_reset_o,
|
|
output reg ext_reset_o,
|
output cpu_enb_o,
|
output cpu_enb_o,
|
output reg a31_o,
|
output reg a31_o,
|
|
|
input bus_error_i,
|
input bus_error_i,
|
input [31:0] bus_error_addr_bi,
|
input [31:0] bus_error_addr_bi,
|
| Line 103... |
Line 105... |
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
begin
|
begin
|
|
|
cpu_reset_o <= CPU_RESET_DEFAULT;
|
cpu_reset_o <= CPU_RESET_DEFAULT;
|
|
ext_reset_o <= EXT_RESET_DEFAULT;
|
a31_o <= A31_DEFAULT;
|
a31_o <= A31_DEFAULT;
|
|
|
trap_enable <= 1'b0;
|
trap_enable <= 1'b0;
|
trap_addr <= 32'h0;
|
trap_addr <= 32'h0;
|
|
|
| Line 139... |
Line 142... |
|
|
if (bus_enb_i == 1'b1)
|
if (bus_enb_i == 1'b1)
|
begin
|
begin
|
if (bus_we_i == 1'b0)
|
if (bus_we_i == 1'b0)
|
case (bus_addr_bi[7:0])
|
case (bus_addr_bi[7:0])
|
REG_CPU_CONTROL_ADDR: bus_rdata_bo <= {cpu_present_i, 29'h0, cpu_break_i, cpu_reset_o};
|
REG_CPU_CONTROL_ADDR: bus_rdata_bo <= {cpu_present_i, 28'h0, cpu_break_i, ext_reset_o, cpu_reset_o};
|
REG_CPU_PC_ADDR: bus_rdata_bo <= cpu_pc_bi;
|
REG_CPU_PC_ADDR: bus_rdata_bo <= cpu_pc_bi;
|
REG_A31: bus_rdata_bo <= {31'h0, a31_o};
|
REG_A31: bus_rdata_bo <= {31'h0, a31_o};
|
|
|
REG_INTC_CONTROL_ADDR: bus_rdata_bo <= {31'h0, intc_ie_i};
|
REG_INTC_CONTROL_ADDR: bus_rdata_bo <= {31'h0, intc_ie_i};
|
REG_INTC_MASK_ADDR: bus_rdata_bo <= {24'h0, intc_mask_bo};
|
REG_INTC_MASK_ADDR: bus_rdata_bo <= {24'h0, intc_mask_bo};
|
| Line 160... |
Line 163... |
REG_BUS_ERROR_ADDR_ADDR: bus_rdata_bo <= bus_error_addr;
|
REG_BUS_ERROR_ADDR_ADDR: bus_rdata_bo <= bus_error_addr;
|
REG_BUS_ERROR_PC_ADDR: bus_rdata_bo <= bus_error_pc;
|
REG_BUS_ERROR_PC_ADDR: bus_rdata_bo <= bus_error_pc;
|
endcase
|
endcase
|
else
|
else
|
case (bus_addr_bi[7:0])
|
case (bus_addr_bi[7:0])
|
REG_CPU_CONTROL_ADDR: cpu_reset_o <= bus_wdata_bi[0];
|
REG_CPU_CONTROL_ADDR: begin cpu_reset_o <= bus_wdata_bi[0]; ext_reset_o <= bus_wdata_bi[1]; end
|
REG_A31: a31_o <= bus_wdata_bi[0];
|
REG_A31: a31_o <= bus_wdata_bi[0];
|
|
|
REG_INTC_CONTROL_ADDR: begin intc_ie_we_o <= 1'b1; intc_ie_data_o <= bus_wdata_bi[0]; end
|
REG_INTC_CONTROL_ADDR: begin intc_ie_we_o <= 1'b1; intc_ie_data_o <= bus_wdata_bi[0]; end
|
REG_INTC_MASK_ADDR: intc_mask_bo <= bus_wdata_bi[7:0];
|
REG_INTC_MASK_ADDR: intc_mask_bo <= bus_wdata_bi[7:0];
|
REG_INTC_REQ_ADDR: begin intc_clr_cmd_o <= 1'b1; intc_clr_code_bo <= bus_wdata_bi[7:0]; end
|
REG_INTC_REQ_ADDR: begin intc_clr_cmd_o <= 1'b1; intc_clr_code_bo <= bus_wdata_bi[7:0]; end
|
