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[/] [pss/] [trunk/] [pss/] [hdl/] [pss/] [zpu_uc/] [zpu_uc.v] - Diff between revs 2 and 5

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Line 2... Line 2... 
 PSS
 
 PSS
 
 
 
 
 
 Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
 
 Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
 
 All rights reserved.
 
 All rights reserved.
 
 
 
 
 
 Version 0.9
 
 Version 0.9.0
 
 
 
 
 
 The FreeBSD license
 
 The FreeBSD license
 
 
 
 
 
 Redistribution and use in source and binary forms, with or without
 
 Redistribution and use in source and binary forms, with or without
 
 modification, are permitted provided that the following conditions
 
 modification, are permitted provided that the following conditions
Line 36... Line 36... 
 
 
 
 
module ZPU_uC
 
module ZPU_uC
 
#(
 
#(
 
        parameter CPU_PRESENT = 1,
 
        parameter CPU_PRESENT = 1,
 
        parameter CPU_RESET_DEFAULT = 1,
 
        parameter CPU_RESET_DEFAULT = 1,
 
        parameter A31_DEFAULTS = 1,
 
        parameter A31_DEFAULT = 1,
 
        parameter MEM_DATA = "data.bin",
 
        parameter MEM_DATA = "data.bin",
 
        parameter MEM_SIZE_KB = 1
 
        parameter MEM_SIZE_KB = 1
 
)
 
)
 
(
 
(
 
        input clk_i, rst_i,
 
        input  clk_i,
 
        input [3:0] INT_i,
 
 
 
 
 
        input  arst_i,
 
 
 
        output srst_o,
 
 
 
        input  srst_i,
 
 
 
        output ext_rst_o,
 
 
 
 
 
 
 
        input [3:0] INT_bi,
 
 
 
 
 
        // Expansion bus
 
        // Expansion bus
 
        output xport_req_o,
 
        output xport_req_o,
 
        input  xport_ack_i,
 
        input  xport_ack_i,
 
        input  xport_err_i,
 
        input  xport_err_i,
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        input  [31:0] dbg_data_bi,
 
        input  [31:0] dbg_data_bi,
 
        output dbg_resp_o,
 
        output dbg_resp_o,
 
        output [31:0] dbg_data_bo
 
        output [31:0] dbg_data_bo
 
);
 
);
 
 
 
 
 
// ZPU system bus
 
wire app_reset;
 
 
 
assign app_reset = srst_i | srst_o;
 
 
 
 
 
 
 
// CPU system bus
 
wire            cpu_bus_enb;
 
wire            cpu_bus_enb;
 
wire            cpu_bus_we;
 
wire            cpu_bus_we;
 
wire            cpu_bus_ack;
 
wire            cpu_bus_ack;
 
wire [31:0] cpu_bus_read;
 
wire [31:0] cpu_bus_read;
 
wire [31:0] cpu_bus_write;
 
wire [31:0] cpu_bus_write;
Line 83... Line 92... 
wire [31:0] ram1_bus_addr;
 
wire [31:0] ram1_bus_addr;
 
wire            ram1_bus_we;
 
wire            ram1_bus_we;
 
wire [31:0] ram1_bus_rddata;
 
wire [31:0] ram1_bus_rddata;
 
wire [31:0] ram1_bus_wrdata;
 
wire [31:0] ram1_bus_wrdata;
 
 
 
 
 
// ZPU control
 
// CPU control
 
wire cpu_present;
 
wire cpu_present;
 
wire [63:0] zpu_status;
 
wire [63:0] zpu_status;
 
wire cpu_break;
 
wire cpu_break;
 
wire [31:0] cpu_pc;
 
wire [31:0] cpu_pc;
 
 
 
 
 
wire            cpu_interrupt;
 
wire            cpu_interrupt;
 
wire            cpu_interrupt_ack;
 
wire            cpu_interrupt_ack;
 
wire            cpu_reset;
 
wire            cpu_reset;
 
wire            cpu_enb;
 
wire            cpu_enb;
 
 
 
 
 
// INTC programming interface
 
 
 
wire            intc_ie;
 
 
 
wire            intc_ie_we;
 
 
 
wire            intc_ie_data;
 
 
 
wire [7:0]  intc_mask;
 
 
 
wire [7:0]       intc_pending;
 
 
 
wire            intc_clr_cmd;
 
 
 
wire [7:0]       intc_clr_code;
 
 
 
 
 
 
 
// interrupts
 
 
 
wire [3:0]  INT;
 
 
 
wire            bus_error_int;
 
 
 
wire            trap_int;
 
 
 
wire            sgi_int;
 
 
 
wire            dma_int;
 
 
 
 
 
 
 
generate
 
generate
 
        if (CPU_PRESENT == 1)
 
        if (CPU_PRESENT == 1)
 
 
 
 
 
// Processor core
 
// Processor core
 
zpu_core
 
zpu_core
Line 121... Line 114... 
        .stack_address((MEM_SIZE_KB * 1024) - 8)
 
        .stack_address((MEM_SIZE_KB * 1024) - 8)
 
)
 
)
 
zpu_core
 
zpu_core
 
(
 
(
 
        .clk(clk_i),
 
        .clk(clk_i),
 
        .sreset(rst_i | cpu_reset),
 
        .sreset(app_reset | cpu_reset),
 
        .enable(cpu_enb),
 
        .enable(cpu_enb),
 
        .cpu_present(cpu_present),
 
        .cpu_present(cpu_present),
 
        .pc_bo(cpu_pc),
 
        .pc_bo(cpu_pc),
 
 
 
 
 
        .mem_req(cpu_bus_enb),
 
        .mem_req(cpu_bus_enb),
Line 145... Line 138... 
        else
 
        else
 
 
 
 
 
zpu_core_stub zpu_core
 
zpu_core_stub zpu_core
 
(
 
(
 
        .clk(clk_i),
 
        .clk(clk_i),
 
        .sreset(rst_i | cpu_reset),
 
        .sreset(app_reset | cpu_reset),
 
        .enable(cpu_enb),
 
        .enable(cpu_enb),
 
        .cpu_present(cpu_present),
 
        .cpu_present(cpu_present),
 
        .pc_bo(cpu_pc),
 
        .pc_bo(cpu_pc),
 
 
 
 
 
        .mem_req(cpu_bus_enb),
 
        .mem_req(cpu_bus_enb),
Line 166... Line 159... 
        .zpu_status(zpu_status)
 
        .zpu_status(zpu_status)
 
);
 
);
 
 
 
 
 
endgenerate
 
endgenerate
 
 
 
 
 
edge_detector edge_det0
 
 
 
( .clk_i(clk_i), .rst_i(rst_i), .in(INT_i[0]), .out(INT[0]) );
 
 
 
 
 
 
 
edge_detector edge_det1
 
 
 
( .clk_i(clk_i), .rst_i(rst_i), .in(INT_i[1]), .out(INT[1]) );
 
 
 
 
 
 
 
edge_detector edge_det2
 
PSS_MotherBlock
 
( .clk_i(clk_i), .rst_i(rst_i), .in(INT_i[2]), .out(INT[2]) );
 
 
 
 
 
 
 
edge_detector edge_det3
 
 
 
( .clk_i(clk_i), .rst_i(rst_i), .in(INT_i[3]), .out(INT[3]) );
 
 
 
 
 
 
 
// Interrupt controller
 
 
 
int_controller int_controller
 
 
 
(
 
 
 
        .clk_i(clk_i),
 
 
 
        .rst_i(rst_i),
 
 
 
        .interrupt_bi({INT, dma_int, sgi_int, trap_int, bus_error_int}),
 
 
 
 
 
 
 
        .ie_o(intc_ie),
 
 
 
        .ie_we_i(intc_ie_we),
 
 
 
        .ie_data_i(intc_ie_data),
 
 
 
        .mask_bi(intc_mask),
 
 
 
        .pending_bo(intc_pending),
 
 
 
        .clr_cmd_i(intc_clr_cmd),
 
 
 
        .clr_code_bi(intc_clr_code),
 
 
 
 
 
 
 
        .cpu_req_o(cpu_interrupt),
 
 
 
        .cpu_ack_i(cpu_interrupt_ack)
 
 
 
);
 
 
 
 
 
 
 
ZPU_uC_SystemController
 
 
 
#(
 
#(
 
        .A31_DEFAULTS(A31_DEFAULTS),
 
        .A31_DEFAULT(A31_DEFAULT),
 
        .CPU_RESET_DEFAULT(CPU_RESET_DEFAULT),
 
        .CPU_RESET_DEFAULT(CPU_RESET_DEFAULT),
 
        .MEM_SIZE_KB(MEM_SIZE_KB)
 
        .MEM_SIZE_KB(MEM_SIZE_KB)
 
)
 
)
 
SystemController
 
MotherBlock
 
(
 
(
 
        .clk_i(clk_i),
 
        .clk_i(clk_i),
 
        .rst_i(rst_i),
 
 
 
 
 
        .arst_i(arst_i),
 
 
 
        .srst_o(srst_o),
 
 
 
        .srst_i(srst_i),
 
 
 
        .ext_rst_o(ext_rst_o),
 
 
 
 
 
 
 
        .INT_bi(INT_bi),
 
 
 
        .cpu_ireq_o(cpu_interrupt),
 
 
 
        .cpu_iack_i(cpu_interrupt_ack),
 
 
 
 
 
        //// Masters ////
 
        //// Masters ////
 
        // Debug bus //
 
        // Debug bus //
 
        .dbg_enb_i(dbg_enb_i),
 
        .dbg_enb_i(dbg_enb_i),
 
        .dbg_we_i(dbg_wr_i),
 
        .dbg_we_i(dbg_wr_i),
Line 249... Line 220... 
        .xport_addr_bo(xport_addr_bo),
 
        .xport_addr_bo(xport_addr_bo),
 
        .xport_wdata_bo(xport_wdata_bo),
 
        .xport_wdata_bo(xport_wdata_bo),
 
        .xport_resp_i(xport_resp_i),
 
        .xport_resp_i(xport_resp_i),
 
        .xport_rdata_bi(xport_rdata_bi),
 
        .xport_rdata_bi(xport_rdata_bi),
 
 
 
 
 
        // INTC bus //
 
        .cpu_present_i(cpu_present),
 
        .intc_ie_i(intc_ie),
 
 
 
        .intc_ie_we_o(intc_ie_we),
 
 
 
        .intc_ie_data_o(intc_ie_data),
 
 
 
        .intc_mask_bo(intc_mask),
 
 
 
        .intc_pending_bi(intc_pending),
 
 
 
        .intc_clr_cmd_o(intc_clr_cmd),
 
 
 
        .intc_clr_code_bo(intc_clr_code),
 
 
 
 
 
 
 
        .cpu_present(cpu_present),
 
 
 
        .cpu_pc_bi(cpu_pc),
 
        .cpu_pc_bi(cpu_pc),
 
        .cpu_break_i(cpu_break),
 
        .cpu_break_i(cpu_break),
 
        .cpu_reset_o(cpu_reset),
 
        .cpu_reset_o(cpu_reset),
 
        .cpu_enb_o(cpu_enb),
 
        .cpu_enb_o(cpu_enb)
 
 
 
 
 
        .bus_error_int_o(bus_error_int),
 
 
 
        .trap_int_o(trap_int),
 
 
 
        .dma_int_o(dma_int),
 
 
 
        .sgi_int_o(sgi_int)
 
 
 
);
 
);
 
 
 
 
 
ram_dual
 
ram_dual
 
#(
 
#(
 
        .mem_data(MEM_DATA),
 
        .mem_data(MEM_DATA),

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