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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`timescale 1ps/1ps
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import tb_clk_pkg::*;
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module
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module
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tb_base
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tb_base
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#(
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#(
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parameter PERIOD = 0,
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N = 1,
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parameter ASSERT_TIME = 0
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realtime PERIODS[N],
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realtime ASSERT_TIME = (PERIODS[0] * 5) + (PERIODS[0] / 3)
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)
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)
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(
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(
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output clock,
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output bit tb_clk[N],
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output reg reset
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output bit tb_aresetn,
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output bit tb_reset[N]
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);
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);
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timeunit 1ns;
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timeprecision 100ps;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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function void assert_reset(realtime reset_assert=ASSERT_TIME);
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task assert_reset
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(
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input time reset_assert
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);
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reset = 1;
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$display( "-#- %16.t | %m | reset asserted!", $time );
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#reset_assert;
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reset = 0;
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$display( "-#- %16.t | %m | reset deasserted!", $time );
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endtask
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// --------------------------------------------------------------------
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//
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task timeout_stop
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(
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input time timeout
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);
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$display("-#- %16.t | %m | timeout_stop at %t", $time, timeout);
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fork
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fork
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#(timeout) $stop;
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begin
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tb_aresetn = 0;
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#reset_assert;
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tb_aresetn = 1;
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end
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join_none
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join_none
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endfunction
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endtask
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// --------------------------------------------------------------------
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bit disable_clks[N];
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generate
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for(genvar j = 0; j < N; j++) begin
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always
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if(disable_clks[j])
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tb_clk[j] = 0;
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else
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#(PERIODS[j]/2) tb_clk[j] = ~tb_clk[j];
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end
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endgenerate
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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generate
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tb_clk_class tb_clk_c;
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for(genvar j = 0; j < N; j++) begin
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tb_clk_if tb_clk_driver();
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bit reset = 1;
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assign clock = tb_clk_driver.clk;
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assign tb_reset[j] = reset;
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time reset_assert = (PERIOD * 5) + (PERIOD / 3);
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logic init_done = 0;
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initial
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begin
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always @(posedge tb_clk[j] or negedge tb_aresetn)
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if(~tb_aresetn)
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reset = 1;
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reset = 1;
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else
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tb_clk_c = new( tb_clk_driver );
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reset = 0;
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if( PERIOD != 0 )
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tb_clk_c.init_basic_clock( PERIOD );
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if( ASSERT_TIME != 0 )
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assert_reset( ASSERT_TIME );
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else if( reset_assert != 0 )
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assert_reset( reset_assert );
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init_done = 1;
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end
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end
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endmodule
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endgenerate
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// --------------------------------------------------------------------
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initial
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assert_reset();
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// --------------------------------------------------------------------
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endmodule
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