URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [RIFFA/] [riffa_chnl_rx.sv] - Diff between revs 32 and 34
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 32 |
Rev 34 |
| Line 31... |
Line 31... |
N // data bus width in bytes
|
N // data bus width in bytes
|
)
|
)
|
(
|
(
|
riffa_chnl_if chnl_in,
|
riffa_chnl_if chnl_in,
|
output rx_done,
|
output rx_done,
|
output reg [31:0] rx_index,
|
output reg [30:0] rx_index,
|
output reg rx_last,
|
output reg rx_last,
|
output reg [31:0] rx_len,
|
output reg [31:0] rx_len,
|
output reg [30:0] rx_off,
|
output reg [30:0] rx_off,
|
output rx_data_ren,
|
output rx_data_ren,
|
output rd_empty,
|
output rd_empty,
|
| Line 46... |
Line 46... |
input reset
|
input reset
|
);
|
);
|
|
|
// --------------------------------------------------------------------
|
// --------------------------------------------------------------------
|
//
|
//
|
localparam RW = (N/4); // width of the bus in 32 bit words
|
|
|
|
|
|
// --------------------------------------------------------------------
|
|
//
|
|
riffa_chnl_rx_fsm
|
riffa_chnl_rx_fsm
|
riffa_chnl_rx_fsm_i
|
riffa_chnl_rx_fsm_i
|
(
|
(
|
.rx(chnl_in.rx),
|
.rx(chnl_in.rx),
|
.rx_data_valid(chnl_in.rx_data_valid),
|
.rx_data_valid(chnl_in.rx_data_valid),
|
| Line 88... |
Line 83... |
//
|
//
|
always_ff @(posedge clk)
|
always_ff @(posedge clk)
|
if(reset | rx_done)
|
if(reset | rx_done)
|
rx_index = 0;
|
rx_index = 0;
|
else if(rd_en)
|
else if(rd_en)
|
rx_index <= rx_index + RW;
|
rx_index <= rx_index + (N/4); // increment by 32 bit words
|
|
|
|
|
// --------------------------------------------------------------------
|
// --------------------------------------------------------------------
|
//
|
//
|
assign rx_data_ren = ~wr_full;
|
assign rx_data_ren = ~wr_full;
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.