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[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [RIFFA/] [riffa_chnl_rx.sv] - Diff between revs 34 and 35

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Rev 34	Rev 35
Line 29...	Line 29...
`riffa_chn_rx`	`riffa_chn_rx`
`#(`	`#(`
`N // data bus width in bytes`	`N // data bus width in bytes`
`)`	`)`
`(`	`(`
`riffa_chnl_if chnl_in,`	`riffa_chnl_if chnl_bus,`
	`input rx_ready,`
`output rx_done,`	`output rx_done,`
`output reg [30:0] rx_index,`	`output reg [30:0] rx_index,`
`output reg rx_last,`	`output reg rx_last,`
`output reg [31:0] rx_len,`	`output reg [31:0] rx_len,`
`output reg [30:0] rx_off,`	`output reg [30:0] rx_off,`
`output rx_data_ren,`	`// output rx_data_ren, // shouldn't be here??`
`output rd_empty,`	`output rd_empty,`
`output [(8*N)-1:0] rd_data,`	`output [(8*N)-1:0] rd_data,`
`input rd_en,`	`input rd_en,`

`input clk,`	`input clk,`
Line 49...	Line 50...
`// --------------------------------------------------------------------`	`// --------------------------------------------------------------------`
`//`	`//`
`riffa_chnl_rx_fsm`	`riffa_chnl_rx_fsm`
`riffa_chnl_rx_fsm_i`	`riffa_chnl_rx_fsm_i`
`(`	`(`
`.rx(chnl_in.rx),`	`.rx(chnl_bus.rx),`
`.rx_data_valid(chnl_in.rx_data_valid),`	`.rx_data_valid(chnl_bus.rx_data_valid),`
`.rx_ack(chnl_in.rx_ack),`	`.rx_ack(chnl_bus.rx_ack),`
`.*`	`.*`
`);`	`);`


`// --------------------------------------------------------------------`	`// --------------------------------------------------------------------`
`//`	`//`
`always_ff @(posedge clk)`	`always_ff @(posedge clk)`
`if(chnl_in.rx & chnl_in.rx_ack)`	`if(chnl_bus.rx & chnl_bus.rx_ack)`
`begin`	`begin`
`rx_last <= chnl_in.rx_last;`	`rx_last <= chnl_bus.rx_last;`
`rx_len <= chnl_in.rx_len;`	`rx_len <= chnl_bus.rx_len;`
`rx_off <= chnl_in.rx_off;`	`rx_off <= chnl_bus.rx_off;`
`end`	`end`


`// --------------------------------------------------------------------`	`// --------------------------------------------------------------------`
`//`	`//`
`wire [(8*N)-1:0] wr_data = chnl_in.rx_data;`	`wire [(8*N)-1:0] wr_data = chnl_bus.rx_data;`
`wire wr_full;`	`wire wr_full;`
`wire wr_en = chnl_in.rx_data_ren & chnl_in.rx_data_valid;`	`wire wr_en = chnl_bus.rx_data_ren & chnl_bus.rx_data_valid;`

`tiny_sync_fifo #(.W((8*N)))`	`tiny_sync_fifo #(.W((8*N)))`
`tiny_sync_fifo_i(.*);`	`tiny_sync_fifo_i(.*);`


Line 88...	Line 89...
`rx_index <= rx_index + (N/4); // increment by 32 bit words`	`rx_index <= rx_index + (N/4); // increment by 32 bit words`


`// --------------------------------------------------------------------`	`// --------------------------------------------------------------------`
`//`	`//`
`assign rx_data_ren = ~wr_full;`	`// assign rx_data_ren = ~wr_full; // shouldn't be here??`
	`assign chnl_bus.rx_data_ren = ~wr_full;`


`// --------------------------------------------------------------------`	`// --------------------------------------------------------------------`
`//`	`//`
`endmodule`	`endmodule`

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[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [RIFFA/] [riffa_chnl_rx.sv] - Diff between revs 34 and 35