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[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [RIFFA/] [riffa_chnl_tx.sv] - Diff between revs 32 and 34
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| Rev 32 |
Rev 34 |
| Line 26... |
Line 26... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module
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module
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riffa_chn_tx
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riffa_chn_tx
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#(
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#(
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N, // data bus width in bytes
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N // data bus width in bytes
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D = 2 // TX data fifo depth
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)
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)
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(
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(
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riffa_chnl_if chnl_in,
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riffa_chnl_if chnl_in,
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input tx_ready,
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input tx_ready,
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input tx_done,
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input tx_done,
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output reg [31:0] tx_index,
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output acked,
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output reg [30:0] tx_index,
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input tx_last,
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input tx_last,
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input [31:0] tx_len,
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input [31:0] tx_len,
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input [30:0] tx_off,
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input [30:0] tx_off,
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input clk,
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input clk,
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input reset
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input reset
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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localparam RW = (N/4); // width of the bus in 32 bit words
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// --------------------------------------------------------------------
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//
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riffa_chnl_tx_fsm
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riffa_chnl_tx_fsm
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riffa_chnl_tx_fsm_i
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riffa_chnl_tx_fsm_i
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(
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(
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.tx(chnl_in.tx),
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.tx(chnl_in.tx),
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.tx_ack(chnl_in.tx_ack),
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.tx_ack(chnl_in.tx_ack),
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Line 56... |
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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always_ff @(posedge clk)
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always_ff @(posedge clk)
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if(reset | ~chnl_in.tx)
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if(reset | ~chnl_in.tx | tx_done)
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tx_index = 0;
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tx_index = 0;
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else if(chnl_in.tx_data_valid & chnl_in.tx_data_ren)
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else if(chnl_in.tx_data_valid & chnl_in.tx_data_ren)
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tx_index <= tx_index + RW;
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tx_index <= tx_index + (N/4); // increment by 32 bit words
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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endmodule
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endmodule
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