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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module
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module
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riffa_register_file
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riffa_register_file
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#(
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#(
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A, // address bus width
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N, // data bus width in bytes
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N, // data bus width in bytes
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MW = 3 // mux select width
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B // number of register banks
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)
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)
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(
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(
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riffa_chnl_if chnl_in,
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riffa_chnl_if chnl_in,
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riffa_register_if r_if,
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riffa_register_if r_if,
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input clk, // must be same clock domain as rx_clk & tx_clk
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input clk, // must be same clock domain as rx_clk & tx_clk
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// synthesis translate_off
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// synthesis translate_off
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initial
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initial
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begin
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a_data_bus_mod: assert(N % 4 == 0) else $fatal;
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a_data_bus_mod: assert(N % 4 == 0) else $fatal;
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a_data_bus_power_of_2: assert((N != 0) & ((N & (N - 1)) == 0)) else $fatal;
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end
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// synthesis translate_on
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// synthesis translate_on
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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localparam RW = (N/4); // width of the bus in 32 bit words
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localparam RW = (N/4); // width of the bus in 32 bit words
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localparam MI = 2 ** MW; // mux inputs
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localparam RC = RW * B; // number of available registers
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localparam LB = $clog2(RW);
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localparam UB = LB + MW;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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wire rx_ready = ~reset;
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wire rx_done;
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wire rx_done;
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wire [31:0] rx_index;
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wire [30:0] rx_index;
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wire rx_last;
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wire rx_last;
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wire [31:0] rx_len;
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wire [31:0] rx_len;
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wire [30:0] rx_off;
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wire [30:0] rx_off; // offset ignored, always start from offset 0
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wire rx_data_ren;
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// wire rx_data_ren;
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wire rd_empty;
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wire rd_empty;
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wire [(8*N)-1:0] rd_data;
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wire [(8*N)-1:0] rd_data;
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wire rd_en;
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wire rd_en;
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riffa_chn_rx #(.N(N))
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riffa_chn_rx #(.N(N))
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riffa_chn_rx_i(.*);
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riffa_chn_rx_i(.chnl_bus(chnl_in), .*);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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wire register_select [MI-1:0];
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wire register_select [RC-1:0];
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genvar j;
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genvar j, k;
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generate
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generate
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for(j = 0; j < MI; j = j + 1)
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for(j = 0; j < B; j = j + 1)
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begin: decoder_gen
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begin: register_j_gen
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assign register_select[j] = (rx_index[UB:LB] == j) & (rx_index[31:UB] == 0) ? 1 : 0;
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for(k = 0; k < RW; k = k + 1)
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begin: register_k_gen
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assign register_select[(j*RW) + k] = (rx_index[30:$clog2(RW)] == j);
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always_ff @(posedge clk)
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always_ff @(posedge clk)
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if(reset)
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if(reset)
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r_if.register_out[j] <= 0;
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r_if.register_out[(j*RW) + k] <= 0;
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else if(rd_en & register_select[j])
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else if(rd_en & register_select[(j*RW) + k])
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r_if.register_out[j] <= rd_data;
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r_if.register_out[(j*RW) + k] <= rd_data[k*32 +: 32];
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end
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end
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end
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endgenerate
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endgenerate
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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assign chnl_in.rx_data_ren = rx_data_ren;
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// assign chnl_in.rx_data_ren = rx_data_ren;
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assign rd_en = ~rd_empty;
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assign rd_en = ~rd_empty;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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wire tx_ready = 1;
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wire tx_ready = 1;
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wire tx_last = 1;
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wire tx_last = 1;
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wire [31:0] tx_len = RW*MI;
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wire acked;
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wire [31:0] tx_len = RC;
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wire [30:0] tx_off = 0;
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wire [30:0] tx_off = 0;
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wire [31:0] tx_index;
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wire [30:0] tx_index;
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wire tx_done = (tx_index >= chnl_in.tx_len - RW);
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wire tx_done = (tx_index >= chnl_in.tx_len - RW);
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riffa_chn_tx #(.N(N))
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riffa_chn_tx #(.N(N))
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riffa_chn_tx_i(.*);
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riffa_chn_tx_i(.*);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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recursive_mux #(.A(MW), .W(N*8))
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wire [(N*8)-1:0] data_in [(2 ** $clog2(B))-1:0];
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generate
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for(j = 0; j < B; j = j + 1)
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begin: data_in_j_gen
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for(k = 0; k < RW; k = k + 1)
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begin: data_in_k_gen
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assign data_in[j][k*32 +: 32] = r_if.register_out[(j*RW) + k];
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end
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end
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endgenerate
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// --------------------------------------------------------------------
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//
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recursive_mux #(.A($clog2(B)), .W(N*8))
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recursive_mux_i
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recursive_mux_i
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(
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(
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.select(tx_index[UB:LB]),
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.select(tx_index[$clog2(B) + $clog2(RW) - 1:$clog2(RW)]),
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.data_in(r_if.register_in),
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.data_out(chnl_in.tx_data),
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.data_out(chnl_in.tx_data)
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.*
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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assign chnl_in.rx_clk = clk;
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assign chnl_in.rx_clk = clk;
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assign chnl_in.tx_clk = clk;
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assign chnl_in.tx_clk = clk;
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assign chnl_in.rx_reset = reset;
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assign chnl_in.rx_reset = reset;
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assign chnl_in.tx_reset = reset;
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assign chnl_in.tx_reset = reset;
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assign chnl_in.tx_last = 1;
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assign chnl_in.tx_last = 1;
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assign chnl_in.tx_len = RW*MI;
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assign chnl_in.tx_len = RC;
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assign chnl_in.tx_off = 0;
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assign chnl_in.tx_off = 0;
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assign chnl_in.tx_data_valid = 1;
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assign chnl_in.tx_data_valid = acked;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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endmodule
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endmodule
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