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module
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module
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axi4_lite_register_file
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axi4_lite_register_file
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#(
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#(
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A = 32, // address bus width, must be 32 or greater for axi lite
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A = 32, // address bus width, must be 32 or greater for axi lite
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N = 8, // data bus width in bytes, must be 4 or 8 for axi lite
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N = 8, // data bus width in bytes, must be 4 or 8 for axi lite
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I = 1 // ID width
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I = 1, // ID width
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MW = 3 // mux select width
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)
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)
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(
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(
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axi4_if axi4_s,
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axi4_if axi4_s,
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axi4_lite_register_if r_if,
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axi4_lite_register_if r_if,
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input aclk,
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input aclk,
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input aresetn
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input aresetn
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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localparam MI = 2 ** MW; // mux inputs
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localparam LB = (N == 8) ? 3 : 2;
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localparam LB = (N == 8) ? 3 : 2;
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localparam UB = LB + r_if.MW - 1;
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localparam UB = LB + MW - 1;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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wire aw_rd_empty;
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wire aw_rd_empty;
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Line 58... |
wire b_wr_en = rf_wr_en;
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wire b_wr_en = rf_wr_en;
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axi4_if #(.A(A), .N(N), .I(I))
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axi4_if #(.A(A), .N(N), .I(I))
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axi4_write_fifo(.*);
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axi4_write_fifo(.*);
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axi4_to_write_fifos #(.A(A), .N(N), .I(I), .USE_ADVANCED_PROTOCOL(0))
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axi4_s_to_write_fifos #(.A(A), .N(N), .I(I), .USE_ADVANCED_PROTOCOL(0))
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axi4_to_write_fifos_i(.*);
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axi4_s_to_write_fifos_i(.*);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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wire register_select [r_if.MI-1:0];
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wire register_select [MI-1:0];
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genvar j;
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genvar j;
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generate
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generate
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for(j = 0; j < r_if.MI; j = j + 1)
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for(j = 0; j < MI; j = j + 1)
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begin: decoder_gen
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begin: decoder_gen
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assign register_select[j] = (axi4_write_fifo.awaddr[UB:LB] == j) ? 1 : 0;
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assign register_select[j] = (axi4_write_fifo.awaddr[UB:LB] == j) ? 1 : 0;
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always_ff @(posedge aclk)
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always_ff @(posedge aclk)
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if(~aresetn)
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if(~aresetn)
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Line 92... |
wire r_wr_en = rf_rd_en;
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wire r_wr_en = rf_rd_en;
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axi4_if #(.A(A), .N(N), .I(I))
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axi4_if #(.A(A), .N(N), .I(I))
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axi4_read_fifo(.*);
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axi4_read_fifo(.*);
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axi4_to_read_fifos #(.A(A), .N(N), .I(I), .USE_ADVANCED_PROTOCOL(0))
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axi4_s_to_read_fifos #(.A(A), .N(N), .I(I), .USE_ADVANCED_PROTOCOL(0))
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axi4_to_read_fifos_i(.*);
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axi4_s_to_read_fifos_i(.*);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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recursive_mux #(.A(r_if.MW), .W(N*8))
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recursive_mux #(.A(MW), .W(N*8))
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recursive_mux_i
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recursive_mux_i
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(
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(
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.select(axi4_read_fifo.araddr[UB:LB]),
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.select(axi4_read_fifo.araddr[UB:LB]),
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.data_in(r_if.register_in),
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.data_in(r_if.register_in),
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.data_out(axi4_read_fifo.rdata)
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.data_out(axi4_read_fifo.rdata)
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