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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module
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module
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axis_gear_box
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axis_gear_box
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#(
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#(
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IN_N = 1, // data bus width in bytes. axis_in.
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IN_N = 2, // data bus width in bytes. axis_in.
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IN_I = 1, // TID width
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OUT_N = 2, // data bus width in bytes. axis_out.
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IN_D = 1, // TDEST width
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IN_W = 16, // width in bits
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IN_U = 1, // TUSER width
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OUT_W = 14, // width in bits
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U = 1, // TUSER width
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USE_TSTRB = 0, // set to 1 to enable, 0 to disable
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USE_TSTRB = 0, // set to 1 to enable, 0 to disable
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USE_TKEEP = 0, // set to 1 to enable, 0 to disable
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USE_TKEEP = 0, // set to 1 to enable, 0 to disable
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ANTECEDENT = 7, // ANTECEDENT:CONSEQUENT ratio
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ANTECEDENT = 7, // in:out ratio (ANTECEDENT:CONSEQUENT)
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CONSEQUENT = 8
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CONSEQUENT = 8
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)
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)
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(
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(
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axis_if axis_in,
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axis_if axis_in,
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axis_if axis_out,
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axis_if axis_out,
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input aresetn
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input aresetn
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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assign axis_in.tready = 1;
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localparam B_W = IN_W*ANTECEDENT;
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localparam UB_W = $clog2(B_W);
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localparam UB_A = $clog2(ANTECEDENT);
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localparam UB_C = $clog2(CONSEQUENT);
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// --------------------------------------------------------------------
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// synthesis translate_off
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initial
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begin
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a_consequent: assert(B_W % CONSEQUENT == 0) else $fatal;
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a_in_w: assert(B_W % IN_W == 0) else $fatal;
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a_out_w: assert(B_W % OUT_W == 0) else $fatal;
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end
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// synthesis translate_on
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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reg [UB_W:0] wr_index;
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reg [UB_A:0] wr_select;
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wire wr_en = axis_in.tvalid & axis_in.tready & aresetn;
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wire wr_end = wr_en & (wr_index == B_W - IN_W);
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wire [UB_W:0] wr_next_index = wr_end ? 0 : wr_index + IN_W;
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always_ff @(posedge aclk)
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if(~aresetn)
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wr_index <= 0;
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else if(wr_en)
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wr_index <= wr_next_index;
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always_ff @(posedge aclk)
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if(~aresetn)
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wr_select <= 0;
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else if(wr_en)
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wr_select <= wr_end ? 0 : wr_select + 1;
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// --------------------------------------------------------------------
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//
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reg [UB_W:0] rd_index;
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reg [UB_C:0] rd_select;
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wire rd_en = axis_out.tvalid & axis_out.tready;
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wire rd_end = rd_en & (rd_index == B_W - OUT_W);
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wire [UB_W:0] rd_next_index = rd_end ? 0 : rd_index + OUT_W;
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always_ff @(posedge aclk)
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if(~aresetn)
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rd_index <= 0;
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else if(rd_en)
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rd_index <= rd_next_index;
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always_ff @(posedge aclk)
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if(~aresetn)
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rd_select <= 0;
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else if(rd_en)
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rd_select <= rd_end ? 0 : rd_select + 1;
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// --------------------------------------------------------------------
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//
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reg [B_W:0] buffer;
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genvar j;
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generate
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begin: buffer_gen
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for(j = 0; j < B_W/IN_W; j++)
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always_ff @(posedge aclk)
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if(wr_en & (wr_select == j))
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buffer[j*IN_W +: IN_W] <= axis_in.tdata[IN_W-1:0];
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end
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endgenerate
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// --------------------------------------------------------------------
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//
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// localparam C_DO = B_W/OUT_W;
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localparam MC_DO = 2**$clog2(CONSEQUENT); // max count
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wire [OUT_W-1:0] data_in[MC_DO-1:0];
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wire [OUT_W-1:0] data_out;
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generate
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begin: data_out_gen
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for(j = 0; j < CONSEQUENT; j++)
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assign data_in[j] = buffer[j*OUT_W +: OUT_W];
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if(MC_DO > CONSEQUENT)
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for(j = CONSEQUENT; j < MC_DO; j++)
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assign data_in[j] = 0;
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end
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endgenerate
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// --------------------------------------------------------------------
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//
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recursive_mux #(.A($clog2(CONSEQUENT)), .W(OUT_W))
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recursive_mux_i(.select(rd_select), .*);
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//---------------------------------------------------
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// state machine binary definitions
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enum reg [1:0]
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{
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SAME = 2'b01,
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WR_LAPPED = 2'b10
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} state, next_state;
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//---------------------------------------------------
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// state machine flop
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always_ff @(posedge aclk)
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if(~aresetn)
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state <= SAME;
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else
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state <= next_state;
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//---------------------------------------------------
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// state machine
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always_comb
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case(state)
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SAME: if(wr_end & ~rd_end)
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next_state <= WR_LAPPED;
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else
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next_state <= SAME;
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WR_LAPPED: if(rd_end & ~wr_end)
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next_state <= SAME;
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else
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next_state <= WR_LAPPED;
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default: next_state <= SAME;
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endcase
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// --------------------------------------------------------------------
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//
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wire empty = (state == SAME) ? rd_next_index > wr_index : 0;
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wire full = (state == SAME) ? 0 : wr_next_index > rd_index;
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assign axis_in.tready = ~full;
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assign axis_out.tvalid = ~empty;
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assign axis_out.tdata = data_out;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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endmodule
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endmodule
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