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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2016 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module
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module
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axis_synchronizer
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axis_synchronizer
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#(
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#(
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N = 8, // data bus width in bytes
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N, // data bus width in bytes
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I = 0, // TID width
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I = 1, // TID width
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D = 0, // TDEST width
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D = 1, // TDEST width
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U = 1, // TUSER width
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U = 1, // TUSER width
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USE_TSTRB = 0, // set to 1 to enable, 0 to disable
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USE_TSTRB = 0, // set to 1 to enable, 0 to disable
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USE_TKEEP = 0 // set to 1 to enable, 0 to disable
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USE_TKEEP = 0, // set to 1 to enable, 0 to disable
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FD
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)
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)
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(
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(
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axis_if axis_in,
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axis_if axis_in,
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axis_if axis_out,
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axis_if axis_out,
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input wr_clk,
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input aclk_in,
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input wr_reset,
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input aresetn_in,
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input aclk,
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input aclk_out,
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input aresetn
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input aresetn_out
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// synthesis translate_off
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initial
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begin
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a_tid_unsuported: assert(I == 0) else $fatal;
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a_tdest_unsuported: assert(D == 0) else $fatal;
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end
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// synthesis translate_on
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1;
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localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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wire rd_empty;
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wire rd_empty;
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wire [W-1:0] rd_data;
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wire [W-1:0] rd_data;
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wire rd_en;
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wire rd_en;
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tiny_async_fifo #(.W(W))
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defparam async_fifo_i.W=W; // why are these needed for recursive modules?
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tiny_async_fifo_i(.rd_clk(aclk), .rd_reset(~aresetn), .*);
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defparam async_fifo_i.D=FD;
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async_fifo
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// async_fifo #(.W(W), .D(FD))
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async_fifo_i
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(
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.wr_clk(aclk_in),
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.wr_reset(~aresetn_in),
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.rd_clk(aclk_out),
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.rd_reset(~aresetn_out),
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.*
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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generate
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defparam axis_map_fifo_i.N=N; // why are these needed for recursive modules?
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begin: assign_gen
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defparam axis_map_fifo_i.I=I;
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if(USE_TSTRB & USE_TKEEP)
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defparam axis_map_fifo_i.D=D;
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begin
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defparam axis_map_fifo_i.U=U;
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assign wr_data =
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defparam axis_map_fifo_i.USE_TSTRB=USE_TSTRB;
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{
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defparam axis_map_fifo_i.USE_TKEEP=USE_TKEEP;
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axis_in.tdata,
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defparam axis_map_fifo_i.W=W;
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axis_in.tlast,
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axis_map_fifo
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axis_in.tuser,
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// #(
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axis_in.tstrb,
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// .N(N),
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axis_in.tkeep
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// .I(I),
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};
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// .D(D),
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assign
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// .U(U),
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{
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// .USE_TSTRB(USE_TSTRB),
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axis_out.tdata,
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// .USE_TKEEP(USE_TKEEP),
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axis_out.tlast,
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// .W(W)
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axis_out.tuser,
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// )
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axis_out.tstrb,
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axis_map_fifo_i(.*);
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axis_out.tkeep
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} = rd_data;
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end
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else if(USE_TSTRB)
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begin
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assign wr_data =
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{
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axis_in.tdata,
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axis_in.tlast,
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axis_in.tuser,
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axis_in.tstrb
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};
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assign
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{
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axis_out.tdata,
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axis_out.tlast,
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axis_out.tuser,
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axis_out.tstrb
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} = rd_data;
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end
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else if(USE_TKEEP)
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begin
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assign wr_data =
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{
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axis_in.tdata,
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axis_in.tlast,
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axis_in.tuser,
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axis_in.tkeep
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};
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assign
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{
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axis_out.tdata,
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axis_out.tlast,
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axis_out.tuser,
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axis_out.tkeep
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} = rd_data;
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end
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else
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begin
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assign wr_data =
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{
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axis_in.tdata,
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axis_in.tlast,
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axis_in.tuser
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};
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assign
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{
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axis_out.tdata,
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axis_out.tlast,
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axis_out.tuser
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} = rd_data;
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end
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end
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endgenerate
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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assign axis_in.tready = ~wr_full;
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assign axis_in.tready = ~wr_full;
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assign wr_en = axis_in.tvalid & axis_in.tready;
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assign wr_en = axis_in.tvalid & ~wr_full;
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assign axis_out.tvalid = ~rd_empty;
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assign axis_out.tvalid = ~rd_empty;
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assign rd_en = axis_out.tvalid & axis_out.tready;
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assign rd_en = axis_out.tready & ~rd_empty;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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endmodule
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endmodule
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