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https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
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Rev 37 |
Line 58... |
Line 58... |
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// Port A
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// Port A
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always @(posedge a_clk)
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always @(posedge a_clk)
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if(a_wr)
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begin
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begin
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a_dout <= mem[a_addr];
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if(a_wr) begin
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a_dout <= a_din;
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a_dout <= a_din;
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mem[a_addr] <= a_din;
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mem[a_addr] <= a_din;
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end
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end
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end
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else
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a_dout <= mem[a_addr];
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// Port B
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// Port B
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always @(posedge b_clk)
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always @(posedge b_clk)
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if(b_wr)
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begin
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begin
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b_dout <= mem[b_addr];
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if(b_wr) begin
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b_dout <= b_din;
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b_dout <= b_din;
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mem[b_addr] <= b_din;
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mem[b_addr] <= b_din;
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end
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end
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end
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else
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b_dout <= mem[b_addr];
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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endmodule
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endmodule
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