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module RAM_wb_sc_dw
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// True dual port RAM as found in ACTEL proasic3 devices
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(
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module ram_sc_dw (d_a, q_a, adr_a, we_a, q_b, adr_b, d_b, we_b, clk);
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d_a,
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q_a,
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parameter dat_width = 32;
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adr_a,
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parameter adr_width = 11;
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we_a,
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parameter mem_size = 2048;
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q_b,
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adr_b,
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input [dat_width-1:0] d_a;
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d_b,
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input [adr_width-1:0] adr_a;
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we_b,
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input [adr_width-1:0] adr_b;
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clk
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);
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parameter DATA_WIDTH = 32;
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parameter ADDR_WIDTH = 11;
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parameter MEM_SIZE = 2048;
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input [(DATA_WIDTH-1):0] d_a;
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input [(ADDR_WIDTH-1):0] adr_a;
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input [(ADDR_WIDTH-1):0] adr_b;
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input we_a;
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input we_a;
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output [(DATA_WIDTH-1):0] q_b;
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output reg [dat_width-1:0] q_b;
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input [(DATA_WIDTH-1):0] d_b;
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input [dat_width-1:0] d_b;
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output reg [(DATA_WIDTH-1):0] q_a;
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output reg [dat_width-1:0] q_a;
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input we_b;
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input we_b;
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input clk;
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input clk;
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reg [(DATA_WIDTH-1):0] q_b;
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reg [DATA_WIDTH-1:0] ram [0:MEM_SIZE - 1] ;
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reg [dat_width-1:0] ram [0:mem_size - 1] ;
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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q_a <= ram[adr_a];
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q_a <= ram[adr_a];
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if (we_a)
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if (we_a)
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ram[adr_a] <= d_a;
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ram[adr_a] <= d_a;
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begin
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begin
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q_b <= ram[adr_b];
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q_b <= ram[adr_b];
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if (we_b)
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if (we_b)
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ram[adr_b] <= d_b;
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ram[adr_b] <= d_b;
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end
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end
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endmodule
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endmodule
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// wrapper for the above dual port RAM
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module ram (dat_i, dat_o, adr_i, we_i, rst, clk );
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parameter dat_width = 32;
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parameter adr_width = 11;
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parameter mem_size = 2048;
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input [dat_width-1:0] dat_i;
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input [adr_width-1:0] adr_i;
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input we_i;
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output [dat_width-1:0] dat_o;
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input rst;
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input clk;
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reg sel;
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wire [dat_width-1:0] q_a, q_b;
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// when adr_i[adr_width-1] = 0 => use a side
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// when adr_i[adr_width-1] = 1 => use b side
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// delay one clock cycle since read has one pipeline stage
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always @ (posedge clk or posedge rst)
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if (rst)
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sel <= 1'b0;
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else
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sel <= adr_i[adr_width-1];
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assign dat_o = !sel ? q_a : q_b;
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ram_sc_dw
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#
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(
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.dat_width(dat_width),
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.adr_width(adr_width-1),
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.mem_size(mem_size/2)
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)
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ram0
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(
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.d_a(dat_i),
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.q_a(q_a),
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.adr_a(adr_i[adr_width-2:0]),
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.we_a(we_i & !adr_i[adr_width-1]),
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.q_b(q_b),
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.adr_b(adr_i[adr_width-2:0]),
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.d_b(dat_i),
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.we_b(we_i & adr_i[adr_width-1]),
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.clk(clk)
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);
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endmodule // ram
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