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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64Div.v] - Diff between revs 3 and 44

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Rev 3 Rev 44
Line 22... Line 22...
// ============================================================================
// ============================================================================
//
//
module Raptor64Div(rst, clk, ld, sgn, isDivi, a, b, imm, qo, ro, dvByZr, done);
module Raptor64Div(rst, clk, ld, sgn, isDivi, a, b, imm, qo, ro, dvByZr, done);
parameter DIV=3'd3;
parameter DIV=3'd3;
parameter IDLE=3'd4;
parameter IDLE=3'd4;
parameter DONE=4'd5;
parameter DONE=3'd5;
input clk;
input clk;
input rst;
input rst;
input ld;
input ld;
input sgn;
input sgn;
input isDivi;
input isDivi;
Line 59... Line 59...
        bb <= 64'd0;
        bb <= 64'd0;
        q <= 64'd0;
        q <= 64'd0;
        r <= 64'd0;
        r <= 64'd0;
        qo <= 64'd0;
        qo <= 64'd0;
        ro <= 64'd0;
        ro <= 64'd0;
 
        cnt <= 8'd0;
        state <= IDLE;
        state <= IDLE;
end
end
else
else
begin
begin
if (!cnt_done)
if (!cnt_done)
Line 78... Line 79...
                end
                end
                else begin
                else begin
                        q <= a;
                        q <= a;
                        bb <= isDivi ? imm : b;
                        bb <= isDivi ? imm : b;
                        so <= 1'b0;
                        so <= 1'b0;
 
                        $display("bb=%d", isDivi ? imm : b);
                end
                end
                dvByZr <= isDivi ? imm==64'd0 : b==64'd0;
                dvByZr <= isDivi ? imm==64'd0 : b==64'd0;
                r <= 64'd0;
                r <= 64'd0;
                cnt <= 8'd65;
                cnt <= 8'd65;
                state <= DIV;
                state <= DIV;

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