| Line 1... |
Line 1... |
`include "Raptor64_opcodes.v"
|
`include "Raptor64_opcodes.v"
|
`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
//=============================================================================
|
//=============================================================================
|
// __
|
// __
|
// \\__/ o\ (C) 2011,2012 Robert Finch
|
// \\__/ o\ (C) 2011-2013 Robert Finch, Stratford
|
// \ __ / All rights reserved.
|
// \ __ / All rights reserved.
|
// \/_// robfinch<remove>@opencores.org
|
// \/_// robfinch<remove>@opencores.org
|
// ||
|
// ||
|
//
|
//
|
// Raptor64_BranchHistory.v
|
// Raptor64_BranchHistory.v
|
| Line 28... |
Line 28... |
//
|
//
|
module Raptor64_BranchHistory(rst, clk, advanceX, xIR, pc, xpc, takb, predict_taken);
|
module Raptor64_BranchHistory(rst, clk, advanceX, xIR, pc, xpc, takb, predict_taken);
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
input advanceX;
|
input advanceX;
|
input [41:0] xIR;
|
input [31:0] xIR;
|
input [63:0] pc;
|
input [63:0] pc;
|
input [63:0] xpc;
|
input [63:0] xpc;
|
input takb;
|
input takb;
|
output predict_taken;
|
output predict_taken;
|
|
|
| Line 43... |
Line 43... |
// In the real world we don't care.
|
// In the real world we don't care.
|
initial begin
|
initial begin
|
for (n = 0; n < 256; n = n + 1)
|
for (n = 0; n < 256; n = n + 1)
|
branch_history_table[n] = 0;
|
branch_history_table[n] = 0;
|
end
|
end
|
wire [7:0] bht_wa = {xpc[5:0],gbl_branch_hist[2:1]}; // write address
|
wire [7:0] bht_wa = {xpc[7:2],gbl_branch_hist[2:1]}; // write address
|
wire [7:0] bht_ra1 = {xpc[5:0],gbl_branch_hist[2:1]}; // read address (EX stage)
|
wire [7:0] bht_ra1 = {xpc[7:2],gbl_branch_hist[2:1]}; // read address (EX stage)
|
wire [7:0] bht_ra2 = {pc[5:0],gbl_branch_hist[2:1]}; // read address (IF stage)
|
wire [7:0] bht_ra2 = {pc[7:2],gbl_branch_hist[2:1]}; // read address (IF stage)
|
wire [1:0] bht_xbits = branch_history_table[bht_ra1];
|
wire [1:0] bht_xbits = branch_history_table[bht_ra1];
|
wire [1:0] bht_ibits = branch_history_table[bht_ra2];
|
wire [1:0] bht_ibits = branch_history_table[bht_ra2];
|
assign predict_taken = bht_ibits==2'd0 || bht_ibits==2'd1;
|
assign predict_taken = bht_ibits==2'd0 || bht_ibits==2'd1;
|
|
|
wire [6:0] xOpcode = xIR[41:35];
|
wire [6:0] xOpcode = xIR[31:25];
|
wire isxBranchI = (xOpcode==`BEQI || xOpcode==`BNEI ||
|
wire isxBranchI = (xOpcode==`BEQI || xOpcode==`BNEI ||
|
xOpcode==`BLTI || xOpcode==`BLEI || xOpcode==`BGTI || xOpcode==`BGEI ||
|
xOpcode==`BLTI || xOpcode==`BLEI || xOpcode==`BGTI || xOpcode==`BGEI ||
|
xOpcode==`BLTUI || xOpcode==`BLEUI || xOpcode==`BGTUI || xOpcode==`BGEUI)
|
xOpcode==`BLTUI || xOpcode==`BLEUI || xOpcode==`BGTUI || xOpcode==`BGEUI)
|
;
|
;
|
wire isxBranch = isxBranchI || xOpcode==`TRAPcc || xOpcode==`TRAPcci || xOpcode==`BTRI || xOpcode==`BTRR;
|
wire isxBranch = isxBranchI || xOpcode==`TRAPcc || xOpcode==`TRAPcci || xOpcode==`BTRI || xOpcode==`BTRR;
|
