| Line 26... |
Line 26... |
// If a register field is not used by an instruction, then the register
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// If a register field is not used by an instruction, then the register
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// selected is forced to r0 for that field. This causes load stalls to be
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// selected is forced to r0 for that field. This causes load stalls to be
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// avoided, which would otherwise occur.
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// avoided, which would otherwise occur.
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//=============================================================================
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//=============================================================================
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module Raptor64_SetOperandRegs(rst, clk, advanceI, advanceR, advanceX, b, AXC, xAXC, insn, xIR, dRa, dRb, dRc);
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module Raptor64_SetOperandRegs(rst, clk, advanceI, advanceR, advanceX, b, AXC, xAXC, insn, xIR, dRa, dRb, dRc, nxt_Ra, nxt_Rb, nxt_Rc);
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input rst;
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input rst;
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input clk;
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input clk;
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input advanceI;
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input advanceI;
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input advanceR;
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input advanceR;
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input advanceX;
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input advanceX;
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| Line 43... |
Line 43... |
reg [8:0] dRa;
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reg [8:0] dRa;
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output [8:0] dRb;
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output [8:0] dRb;
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reg [8:0] dRb;
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reg [8:0] dRb;
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output [8:0] dRc;
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output [8:0] dRc;
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reg [8:0] dRc;
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reg [8:0] dRc;
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output [8:0] nxt_Ra;
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reg [8:0] nxt_Ra;
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output [8:0] nxt_Rb;
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reg [8:0] nxt_Rb;
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output [8:0] nxt_Rc;
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reg [8:0] nxt_Rc;
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wire [6:0] iOpcode = insn[31:25];
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wire [6:0] iOpcode = insn[31:25];
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wire [6:0] xOpcode = xIR[31:25];
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wire [6:0] xOpcode = xIR[31:25];
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wire [5:0] xFunc = xIR[5:0];
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wire [5:0] xFunc = xIR[5:0];
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wire [6:0] iFunc7 = insn[6:0];
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wire [6:0] iFunc7 = insn[6:0];
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always @(posedge clk)
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if (rst) begin
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always @*
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dRa <= 9'd0;
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begin
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dRb <= 9'd0;
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nxt_Ra <= dRa;
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dRc <= 9'd0;
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nxt_Rb <= dRb;
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end
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nxt_Rc <= dRc;
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else begin
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if (advanceI) begin
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if (advanceI) begin
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// Default settings, to be overridden
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// Default settings, to be overridden
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dRa <= {AXC,insn[24:20]};
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nxt_Ra <= {AXC,insn[24:20]};
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dRb <= {AXC,insn[19:15]};
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nxt_Rb <= {AXC,insn[19:15]};
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dRc <= {AXC,insn[14:10]};
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nxt_Rc <= {AXC,insn[14:10]};
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casex(iOpcode)
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casex(iOpcode)
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`MISC:
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`MISC:
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case(iFunc7)
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case(iFunc7)
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`IRET: begin
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`IRET: begin
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dRa <= {AXC,5'd25};
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nxt_Ra <= {AXC,5'd25};
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dRb <= 9'd0;
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nxt_Rb <= 9'd0;
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dRc <= 9'd0;
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nxt_Rc <= 9'd0;
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end
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end
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`ERET: begin
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`ERET: begin
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dRa <= {AXC,5'd24};
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nxt_Ra <= {AXC,5'd24};
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dRb <= 9'd0;
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nxt_Rb <= 9'd0;
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dRc <= 9'd0;
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nxt_Rc <= 9'd0;
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end
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end
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default:
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default:
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begin
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begin
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dRa <= 9'd0;
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nxt_Ra <= 9'd0;
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dRb <= 9'd0;
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nxt_Rb <= 9'd0;
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dRc <= 9'd0;
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nxt_Rc <= 9'd0;
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end
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end
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endcase
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endcase
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`R: begin dRb <= 9'd0; dRc <= 9'd0; end
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`R: begin nxt_Rb <= 9'd0; nxt_Rc <= 9'd0; end
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`RR: dRc <= 9'd0;
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`RR: nxt_Rc <= 9'd0;
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`TRAPcc: dRc <= 9'd0;
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`TRAPcc: nxt_Rc <= 9'd0;
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`TRAPcci: begin dRb <= 9'd0; dRc <= 9'd0; end
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`TRAPcci: begin nxt_Rb <= 9'd0; nxt_Rc <= 9'd0; end
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`CALL,`JMP,`NOPI:
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`CALL,`JMP,`NOPI:
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begin
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begin
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dRa <= 9'd0;
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nxt_Ra <= 9'd0;
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dRb <= 9'd0;
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nxt_Rb <= 9'd0;
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dRc <= 9'd0;
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nxt_Rc <= 9'd0;
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end
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end
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`RET: begin
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`RET: begin
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dRa <= {AXC,5'd30};
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nxt_Ra <= {AXC,5'd30};
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dRb <= {AXC,5'd31};
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nxt_Rb <= {AXC,5'd31};
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dRc <= 9'd0;
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nxt_Rc <= 9'd0;
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end
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end
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`LB,`LBU,`LH,`LHU,`LC,`LCU,`LW,`LP,`LSH,`LSW,`LF,`LFD,`LFP,`LFDP,`LWR:
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`LB,`LBU,`LH,`LHU,`LC,`LCU,`LW,`LP,`LSH,`LSW,`LF,`LFD,`LFP,`LFDP,`LWR:
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begin
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begin
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dRb <= 9'd0;
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nxt_Rb <= 9'd0;
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dRc <= 9'd0;
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nxt_Rc <= 9'd0;
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end
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end
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`SB,`SC,`SH,`SW,`SP,`SSH,`SSW,`SF,`SFD,`SFP,`SFDP,`SWC:
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`SB,`SC,`SH,`SW,`SP,`SSH,`SSW,`SF,`SFD,`SFP,`SFDP,`SWC:
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dRc <= 9'd0;
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nxt_Rc <= 9'd0;
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`INB,`INBU,`INCH,`INCU,`INH,`INHU,`INW:
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`INB,`INBU,`INCH,`INCU,`INH,`INHU,`INW:
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begin
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begin
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dRb <= 9'd0;
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nxt_Rb <= 9'd0;
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dRc <= 9'd0;
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nxt_Rc <= 9'd0;
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end
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end
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`OUTB,`OUTC,`OUTH,`OUTW:
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`OUTB,`OUTC,`OUTH,`OUTW:
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dRc <= 9'd0;
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nxt_Rc <= 9'd0;
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`BLTI,`BLEI,`BGTI,`BGEI,
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`BLTI,`BLEI,`BGTI,`BGEI,
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`BLTUI,`BLEUI,`BGTUI,`BGEUI,
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`BLTUI,`BLEUI,`BGTUI,`BGEUI,
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`BEQI,`BNEI:
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`BEQI,`BNEI:
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begin
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begin
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dRb <= 9'd0;
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nxt_Rb <= 9'd0;
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dRc <= 9'd0;
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nxt_Rc <= 9'd0;
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end
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end
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`BTRI: dRc <= 9'd0;
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`BTRI: nxt_Rc <= 9'd0;
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`SLTI,`SLEI,`SGTI,`SGEI,
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`SLTI,`SLEI,`SGTI,`SGEI,
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`SLTUI,`SLEUI,`SGTUI,`SGEUI,
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`SLTUI,`SLEUI,`SGTUI,`SGEUI,
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`SEQI,`SNEI:
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`SEQI,`SNEI:
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begin
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begin
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dRb <= 9'd0;
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nxt_Rb <= 9'd0;
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dRc <= 9'd0;
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nxt_Rc <= 9'd0;
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end
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end
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`ADDI,`ADDUI,`SUBI,`SUBUI,`CMPI,`CMPUI,
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`ADDI,`ADDUI,`SUBI,`SUBUI,`CMPI,`CMPUI,
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`ANDI,`XORI,`ORI,`MULUI,`MULSI,`DIVUI,`DIVSI:
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`ANDI,`XORI,`ORI,`MULUI,`MULSI,`DIVUI,`DIVSI:
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begin
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begin
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dRb <= 9'd0;
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nxt_Rb <= 9'd0;
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dRc <= 9'd0;
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nxt_Rc <= 9'd0;
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end
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end
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`JAL:
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`JAL:
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begin
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begin
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dRb <= 9'd0;
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nxt_Rb <= 9'd0;
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dRc <= 9'd0;
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nxt_Rc <= 9'd0;
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end
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end
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`SETLO: begin dRa <= {AXC,insn[26:22]}; dRb <= 9'd0; dRc <= 9'd0; end
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`SETLO: begin nxt_Ra <= {AXC,insn[26:22]}; nxt_Rb <= 9'd0; nxt_Rc <= 9'd0; end
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`SETMID: begin dRa <= {AXC,insn[26:22]}; dRb <= 9'd0; dRc <= 9'd0; end
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`SETMID: begin nxt_Ra <= {AXC,insn[26:22]}; nxt_Rb <= 9'd0; nxt_Rc <= 9'd0; end
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`SETHI: begin dRa <= {AXC,insn[26:22]}; dRb <= 9'd0; dRc <= 9'd0; end
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`SETHI: begin nxt_Ra <= {AXC,insn[26:22]}; nxt_Rb <= 9'd0; nxt_Rc <= 9'd0; end
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default: dRa <= {AXC,insn[24:20]};
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default: nxt_Ra <= {AXC,insn[24:20]};
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endcase
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endcase
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end
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end
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else if (advanceR) begin
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else if (advanceR) begin
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dRa <= 9'd0;
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nxt_Ra <= 9'd0;
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dRb <= 9'd0;
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nxt_Rb <= 9'd0;
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dRc <= 9'd0;
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nxt_Rc <= 9'd0;
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end
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end
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// no else here
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// no else here
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if (advanceX) begin
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if (advanceX) begin
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if (xOpcode==`R) begin
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if (xOpcode==`R) begin
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if (xFunc==`EXEC) begin
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if (xFunc==`EXEC) begin
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dRa <= {xAXC,b[24:20]};
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nxt_Ra <= {xAXC,b[24:20]};
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dRb <= {xAXC,b[19:15]};
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nxt_Rb <= {xAXC,b[19:15]};
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dRc <= {xAXC,b[14:10]};
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nxt_Rc <= {xAXC,b[14:10]};
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end
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end
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end
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end
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end
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end
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end
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always @(posedge clk)
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if (rst) begin
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dRa <= 9'd0;
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dRb <= 9'd0;
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dRc <= 9'd0;
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end
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else begin
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dRa <= nxt_Ra;
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dRb <= nxt_Rb;
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dRc <= nxt_Rc;
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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