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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//
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// If a register field is not used by an instruction, then the register
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// selected is forced to r0 for that field. This causes load stalls to be
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// avoided, which would otherwise occur.
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//=============================================================================
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//=============================================================================
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module Raptor64_SetOperandRegs(rst, clk, advanceI, advanceR, advanceX, b, AXC, insn, xIR, dRa, dRb, dRc);
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module Raptor64_SetOperandRegs(rst, clk, advanceI, advanceR, advanceX, b, AXC, insn, xIR, dRa, dRb, dRc);
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input rst;
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input rst;
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input clk;
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input clk;
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input advanceI;
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input advanceI;
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input advanceR;
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input advanceR;
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input advanceX;
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input advanceX;
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input [63:0] b;
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input [63:0] b;
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input [3:0] AXC;
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input [3:0] AXC;
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input [41:0] insn;
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input [31:0] insn;
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input [41:0] xIR;
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input [31:0] xIR;
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output [8:0] dRa;
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output [8:0] dRa;
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reg [8:0] dRa;
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reg [8:0] dRa;
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output [8:0] dRb;
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output [8:0] dRb;
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reg [8:0] dRb;
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reg [8:0] dRb;
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output [8:0] dRc;
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output [8:0] dRc;
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reg [8:0] dRc;
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reg [8:0] dRc;
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wire [6:0] iOpcode = insn[41:35];
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wire [6:0] iOpcode = insn[31:25];
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wire [6:0] xOpcode = xIR[41:35];
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wire [6:0] xOpcode = xIR[31:25];
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wire [6:0] xFunc = xIR[6:0];
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wire [5:0] xFunc = xIR[5:0];
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wire [6:0] iFunc7 = insn[6:0];
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always @(posedge clk)
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always @(posedge clk)
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if (rst) begin
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if (rst) begin
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dRa <= 9'd0;
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dRa <= 9'd0;
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dRb <= 9'd0;
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dRb <= 9'd0;
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dRc <= 9'd0;
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dRc <= 9'd0;
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end
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end
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else begin
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else begin
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if (advanceI) begin
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if (advanceI) begin
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// Default settings, to be overridden
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// Default settings, to be overridden
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dRa <= {AXC,insn[34:30]};
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dRa <= {AXC,insn[24:20]};
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dRb <= {AXC,insn[29:25]};
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dRb <= {AXC,insn[19:15]};
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dRc <= {AXC,insn[24:20]};
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dRc <= {AXC,insn[14:10]};
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casex(iOpcode)
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casex(iOpcode)
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`MISC:
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case(iFunc7)
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`IRET: begin
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dRa <= {AXC,5'd25};
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dRb <= 9'd0;
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dRc <= 9'd0;
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end
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`ERET: begin
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dRa <= {AXC,5'd24};
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dRb <= 9'd0;
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dRc <= 9'd0;
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end
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default:
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begin
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dRa <= 9'd0;
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dRb <= 9'd0;
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dRc <= 9'd0;
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end
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endcase
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`CALL,`JMP,`NOPI:
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begin
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dRa <= 9'd0;
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dRb <= 9'd0;
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dRc <= 9'd0;
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end
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`RET: begin
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`RET: begin
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dRa <= {AXC,5'd30};
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dRa <= {AXC,5'd30};
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dRb <= {AXC,5'd31};
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dRb <= {AXC,5'd31};
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dRc <= 9'd0;
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end
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end
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`SETLO: dRa <= {AXC,insn[36:32]};
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`BLTI,`BLEI,`BGTI,`BGEI,
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`SETHI: dRa <= {AXC,insn[36:32]};
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`BLTUI,`BLEUI,`BGTUI,`BGEUI,
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`SM,`LM:
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`BEQI,`BNEI:
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begin
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begin
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dRa <= {AXC,1'b1,insn[34:31]};
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dRb <= 9'd0;
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casex(insn[30:0])
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dRc <= 9'd0;
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31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1: dRb <= {AXC,5'd1};
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end
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31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxx10: dRb <= {AXC,5'd2};
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`SLTI,`SLEI,`SGTI,`SGEI,
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31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxx100: dRb <= {AXC,5'd3};
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`SLTUI,`SLEUI,`SGTUI,`SGEUI,
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31'bxxxxxxxxxxxxxxxxxxxxxxxxxxx1000: dRb <= {AXC,5'd4};
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`SEQI,`SNEI:
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31'bxxxxxxxxxxxxxxxxxxxxxxxxxx10000: dRb <= {AXC,5'd5};
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begin
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31'bxxxxxxxxxxxxxxxxxxxxxxxxx100000: dRb <= {AXC,5'd6};
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dRb <= 9'd0;
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31'bxxxxxxxxxxxxxxxxxxxxxxxx1000000: dRb <= {AXC,5'd7};
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dRc <= 9'd0;
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31'bxxxxxxxxxxxxxxxxxxxxxxx10000000: dRb <= {AXC,5'd8};
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31'bxxxxxxxxxxxxxxxxxxxxxx100000000: dRb <= {AXC,5'd9};
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31'bxxxxxxxxxxxxxxxxxxxxx1000000000: dRb <= {AXC,5'd10};
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31'bxxxxxxxxxxxxxxxxxxxx10000000000: dRb <= {AXC,5'd11};
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31'bxxxxxxxxxxxxxxxxxxx100000000000: dRb <= {AXC,5'd12};
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31'bxxxxxxxxxxxxxxxxxx1000000000000: dRb <= {AXC,5'd13};
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31'bxxxxxxxxxxxxxxxxx10000000000000: dRb <= {AXC,5'd14};
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31'bxxxxxxxxxxxxxxxx100000000000000: dRb <= {AXC,5'd15};
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31'bxxxxxxxxxxxxxxx1000000000000000: dRb <= {AXC,5'd16};
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31'bxxxxxxxxxxxxxx10000000000000000: dRb <= {AXC,5'd17};
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31'bxxxxxxxxxxxxx100000000000000000: dRb <= {AXC,5'd18};
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31'bxxxxxxxxxxxx1000000000000000000: dRb <= {AXC,5'd19};
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31'bxxxxxxxxxxx10000000000000000000: dRb <= {AXC,5'd20};
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31'bxxxxxxxxxx100000000000000000000: dRb <= {AXC,5'd21};
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31'bxxxxxxxxx1000000000000000000000: dRb <= {AXC,5'd22};
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31'bxxxxxxxx10000000000000000000000: dRb <= {AXC,5'd23};
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31'bxxxxxxx100000000000000000000000: dRb <= {AXC,5'd24};
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31'bxxxxxx1000000000000000000000000: dRb <= {AXC,5'd25};
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31'bxxxxx10000000000000000000000000: dRb <= {AXC,5'd26};
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31'bxxxx100000000000000000000000000: dRb <= {AXC,5'd27};
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31'bxxx1000000000000000000000000000: dRb <= {AXC,5'd28};
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31'bxx10000000000000000000000000000: dRb <= {AXC,5'd29};
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31'bx100000000000000000000000000000: dRb <= {AXC,5'd30};
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31'b1000000000000000000000000000000: dRb <= {AXC,5'd31};
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default: dRb <= {AXC,5'd0};
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endcase
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end
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end
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default: dRa <= {AXC,insn[34:30]};
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`SETLO: dRa <= {AXC,insn[26:22]};
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`SETMID: dRa <= {AXC,insn[26:22]};
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`SETHI: dRa <= {AXC,insn[26:22]};
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default: dRa <= {AXC,insn[24:20]};
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endcase
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endcase
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end
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end
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else if (advanceR) begin
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else if (advanceR) begin
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dRa <= 9'd0;
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dRa <= 9'd0;
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dRb <= 9'd0;
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dRb <= 9'd0;
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end
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end
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// no else here
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// no else here
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if (advanceX) begin
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if (advanceX) begin
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if (xOpcode==`R) begin
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if (xOpcode==`R) begin
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if (xFunc==`EXEC) begin
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if (xFunc==`EXEC) begin
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dRa <= b[34:30];
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dRa <= b[24:20];
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dRb <= b[29:25];
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dRb <= b[19:15];
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dRc <= b[24:20];
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dRc <= b[14:10];
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end
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end
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end
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end
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end
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end
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end
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end
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