OpenCores
URL https://opencores.org/ocsvn/raptor64/raptor64/trunk

Subversion Repositories raptor64

[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_SetOperandRegs.v] - Diff between revs 44 and 45

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 44 Rev 45
Line 26... Line 26... 
// If a register field is not used by an instruction, then the register
 
// If a register field is not used by an instruction, then the register
 
// selected is forced to r0 for that field. This causes load stalls to be
 
// selected is forced to r0 for that field. This causes load stalls to be
 
// avoided, which would otherwise occur.
 
// avoided, which would otherwise occur.
 
//=============================================================================
 
//=============================================================================
 
 
 
 
 
module Raptor64_SetOperandRegs(rst, clk, advanceI, advanceR, advanceX, b, AXC, insn, xIR, dRa, dRb, dRc);
 
module Raptor64_SetOperandRegs(rst, clk, advanceI, advanceR, advanceX, b, AXC, xAXC, insn, xIR, dRa, dRb, dRc);
 
input rst;
 
input rst;
 
input clk;
 
input clk;
 
input advanceI;
 
input advanceI;
 
input advanceR;
 
input advanceR;
 
input advanceX;
 
input advanceX;
 
input [63:0] b;
 
input [63:0] b;
 
input [3:0] AXC;
 
input [3:0] AXC;
 
 
 
input [3:0] xAXC;
 
input [31:0] insn;
 
input [31:0] insn;
 
input [31:0] xIR;
 
input [31:0] xIR;
 
output [8:0] dRa;
 
output [8:0] dRa;
 
reg [8:0] dRa;
 
reg [8:0] dRa;
 
output [8:0] dRb;
 
output [8:0] dRb;
Line 150... Line 151... 
        end
 
        end
 
        // no else here
 
        // no else here
 
        if (advanceX) begin
 
        if (advanceX) begin
 
                if (xOpcode==`R) begin
 
                if (xOpcode==`R) begin
 
                        if (xFunc==`EXEC) begin
 
                        if (xFunc==`EXEC) begin
 
                                dRa <= b[24:20];
 
                                dRa <= {xAXC,b[24:20]};
 
                                dRb <= b[19:15];
 
                                dRb <= {xAXC,b[19:15]};
 
                                dRc <= b[14:10];
 
                                dRc <= {xAXC,b[14:10]};
 
                        end
 
                        end
 
                end
 
                end
 
        end
 
        end
 
end
 
end
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.