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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//
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//=============================================================================
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//=============================================================================
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`define EX_IRQ 9'd449 // interrupt
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`define EX_NMI 9'd510 // non-maskable interrupt
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module Raptor64_SetTargetRegister(rst,clk,advanceR,advanceX,dIR,dAXC,xRt);
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module Raptor64_SetTargetRegister(rst,clk,advanceR,advanceX,dIR,dAXC,xRt);
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input rst;
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input rst;
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input clk;
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input clk;
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input advanceR;
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input advanceR;
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input advanceX;
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input advanceX;
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input [41:0] dIR;
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input [31:0] dIR;
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input [3:0] dAXC;
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input [3:0] dAXC;
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output [8:0] xRt;
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output [8:0] xRt;
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reg [8:0] xRt;
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reg [8:0] xRt;
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wire [6:0] dOpcode = dIR[41:35];
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wire [6:0] dOpcode = dIR[31:25];
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wire [6:0] dFunc = dIR[6:0];
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wire [6:0] dFunc = dIR[6:0];
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always @(posedge clk)
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always @(posedge clk)
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if (rst) begin
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if (rst) begin
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xRt <= 9'd0;
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xRt <= 9'd0;
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end
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end
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else begin
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else begin
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if (advanceR) begin
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if (advanceR) begin
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casex(dOpcode)
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casex(dOpcode)
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`MISC:
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case(dFunc)
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`SYSCALL: xRt <= {dAXC,dIR[24:20]};
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default: xRt <= 9'd0;
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endcase
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`R:
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`R:
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case(dFunc)
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case(dFunc)
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`MTSPR,`CMG,`CMGI,`EXEC:
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`MTSPR,`CMG,`CMGI,`EXEC:
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xRt <= 9'd0;
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xRt <= 9'd0;
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`MYST: xRt <= {dAXC,dIR[19:15]};
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default: xRt <= {dAXC,dIR[19:15]};
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default: xRt <= {dAXC,dIR[29:25]};
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endcase
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endcase
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`SETLO: xRt <= {dAXC,dIR[36:32]};
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`MYST,`MUX: xRt <= {dAXC,dIR[ 9: 5]};
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`SETHI: xRt <= {dAXC,dIR[36:32]};
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`SETLO: xRt <= {dAXC,dIR[26:22]};
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`RR,`FP: xRt <= {dAXC,dIR[24:20]};
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`SETMID: xRt <= {dAXC,dIR[26:22]};
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`SETHI: xRt <= {dAXC,dIR[26:22]};
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`RR,`FP: xRt <= {dAXC,dIR[14:10]};
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`BTRI: xRt <= 9'd0;
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`BTRI: xRt <= 9'd0;
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`BTRR:
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`BTRR:
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case(dIR[4:0])
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case(dIR[4:0])
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`LOOP: xRt <= {dAXC,dIR[29:25]};
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`LOOP: xRt <= {dAXC,dIR[19:15]};
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default: xRt <= 9'd0;
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default: xRt <= 9'd0;
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endcase
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endcase
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`TRAPcc: xRt <= 9'd0;
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`TRAPcc: xRt <= 9'd0;
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`TRAPcci: xRt <= 9'd0;
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`TRAPcci: xRt <= 9'd0;
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`JMP: xRt <= 9'd00;
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`JMP: xRt <= 9'd00;
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`MEMNDX:
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`MEMNDX:
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case(dFunc[5:0])
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case(dFunc[5:0])
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`SWX,`SHX,`SCX,`SBX,`SFX,`SFDX,`SPX,`SFPX,`SFDPX,`SSHX,`SSWX,
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`SWX,`SHX,`SCX,`SBX,`SFX,`SFDX,`SPX,`SFPX,`SFDPX,`SSHX,`SSWX,
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`OUTWX,`OUTHX,`OUTCX,`OUTBX:
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`OUTWX,`OUTHX,`OUTCX,`OUTBX:
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xRt <= 9'd0;
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xRt <= 9'd0;
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default: xRt <= {dAXC,dIR[24:20]};
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default: xRt <= {dAXC,dIR[14:10]};
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endcase
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endcase
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`LSH,`LSW,
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`LSH,`LSW,
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`SW,`SH,`SC,`SB,`SF,`SFD,`SSH,`SSW,`SP,`SFP,`SFDP, // but not SWC!
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`SW,`SH,`SC,`SB,`SF,`SFD,`SSH,`SSW,`SP,`SFP,`SFDP, // but not SWC!
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`OUTW,`OUTH,`OUTC,`OUTB:
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`OUTW,`OUTH,`OUTC,`OUTB:
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xRt <= 9'd0;
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xRt <= 9'd0;
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`NOPI: xRt <= 9'd0;
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`NOPI: xRt <= 9'd0;
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`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
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`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
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xRt <= 9'd0;
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xRt <= 9'd0;
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`SM: xRt <= 9'd0;
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default: xRt <= {dAXC,dIR[19:15]};
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`LM:
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casex(dIR[30:0])
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31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1: xRt <= {dAXC,5'd1};
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31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxx10: xRt <= {dAXC,5'd2};
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31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxx100: xRt <= {dAXC,5'd3};
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31'bxxxxxxxxxxxxxxxxxxxxxxxxxxx1000: xRt <= {dAXC,5'd4};
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31'bxxxxxxxxxxxxxxxxxxxxxxxxxx10000: xRt <= {dAXC,5'd5};
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31'bxxxxxxxxxxxxxxxxxxxxxxxxx100000: xRt <= {dAXC,5'd6};
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31'bxxxxxxxxxxxxxxxxxxxxxxxx1000000: xRt <= {dAXC,5'd7};
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31'bxxxxxxxxxxxxxxxxxxxxxxx10000000: xRt <= {dAXC,5'd8};
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31'bxxxxxxxxxxxxxxxxxxxxxx100000000: xRt <= {dAXC,5'd9};
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31'bxxxxxxxxxxxxxxxxxxxxx1000000000: xRt <= {dAXC,5'd10};
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31'bxxxxxxxxxxxxxxxxxxxx10000000000: xRt <= {dAXC,5'd11};
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31'bxxxxxxxxxxxxxxxxxxx100000000000: xRt <= {dAXC,5'd12};
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31'bxxxxxxxxxxxxxxxxxx1000000000000: xRt <= {dAXC,5'd13};
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31'bxxxxxxxxxxxxxxxxx10000000000000: xRt <= {dAXC,5'd14};
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31'bxxxxxxxxxxxxxxxx100000000000000: xRt <= {dAXC,5'd15};
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31'bxxxxxxxxxxxxxxx1000000000000000: xRt <= {dAXC,5'd16};
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31'bxxxxxxxxxxxxxx10000000000000000: xRt <= {dAXC,5'd17};
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31'bxxxxxxxxxxxxx100000000000000000: xRt <= {dAXC,5'd18};
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31'bxxxxxxxxxxxx1000000000000000000: xRt <= {dAXC,5'd19};
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31'bxxxxxxxxxxx10000000000000000000: xRt <= {dAXC,5'd20};
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31'bxxxxxxxxxx100000000000000000000: xRt <= {dAXC,5'd21};
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31'bxxxxxxxxx1000000000000000000000: xRt <= {dAXC,5'd22};
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31'bxxxxxxxx10000000000000000000000: xRt <= {dAXC,5'd23};
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31'bxxxxxxx100000000000000000000000: xRt <= {dAXC,5'd24};
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31'bxxxxxx1000000000000000000000000: xRt <= {dAXC,5'd25};
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31'bxxxxx10000000000000000000000000: xRt <= {dAXC,5'd26};
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31'bxxxx100000000000000000000000000: xRt <= {dAXC,5'd27};
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31'bxxx1000000000000000000000000000: xRt <= {dAXC,5'd28};
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31'bxx10000000000000000000000000000: xRt <= {dAXC,5'd29};
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31'bx100000000000000000000000000000: xRt <= {dAXC,5'd30};
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31'b1000000000000000000000000000000: xRt <= {dAXC,5'd31};
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default: xRt <= 9'h000;
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endcase
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endcase
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default: xRt <= {dAXC,dIR[29:25]};
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endcase
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if (dOpcode[6:4]==`IMM)
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xRt <= 9'd0;
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end
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end
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else if (advanceX)
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else if (advanceX)
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xRt <= 9'd0;
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xRt <= 9'd0;
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end
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end
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