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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_SetTargetRegister.v] - Diff between revs 41 and 44
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| Rev 41 |
Rev 44 |
| Line 48... |
Line 48... |
else begin
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else begin
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if (advanceR) begin
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if (advanceR) begin
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casex(dOpcode)
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casex(dOpcode)
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`MISC:
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`MISC:
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case(dFunc)
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case(dFunc)
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`SYSCALL: xRt <= {dAXC,dIR[24:20]};
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`SYSCALL: xRt <= 9'd0;
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default: xRt <= 9'd0;
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default: xRt <= 9'd0;
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endcase
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endcase
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`R:
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`R:
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case(dFunc)
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case(dFunc)
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`MTSPR,`CMG,`CMGI,`EXEC:
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`MTSPR,`CMG,`CMGI,`EXEC:
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