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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_SetTargetRegister.v] - Diff between revs 44 and 45

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Rev 44 Rev 45
Line 26... Line 26...
//=============================================================================
//=============================================================================
 
 
`define EX_IRQ                  9'd449  // interrupt
`define EX_IRQ                  9'd449  // interrupt
`define EX_NMI                  9'd510  // non-maskable interrupt
`define EX_NMI                  9'd510  // non-maskable interrupt
 
 
module Raptor64_SetTargetRegister(rst,clk,advanceR,advanceX,dIR,dAXC,xRt);
module Raptor64_SetTargetRegister(rst,clk,advanceR,advanceX,dIR,dIRvalid,dAXC,xRt);
input rst;
input rst;
input clk;
input clk;
input advanceR;
input advanceR;
input advanceX;
input advanceX;
input [31:0] dIR;
input [31:0] dIR;
 
input dIRvalid;
input [3:0] dAXC;
input [3:0] dAXC;
output [8:0] xRt;
output [8:0] xRt;
reg [8:0] xRt;
reg [8:0] xRt;
 
 
wire [6:0] dOpcode = dIR[31:25];
wire [6:0] dOpcode = dIR[31:25];
Line 45... Line 46...
if (rst) begin
if (rst) begin
        xRt <= 9'd0;
        xRt <= 9'd0;
end
end
else begin
else begin
if (advanceR) begin
if (advanceR) begin
 
        if (dIRvalid) begin
        casex(dOpcode)
        casex(dOpcode)
        `MISC:
        `MISC:
                case(dFunc)
                case(dFunc)
                `SYSCALL:       xRt <= 9'd0;
                `SYSCALL:       xRt <= 9'd0;
                default:        xRt <= 9'd0;
                default:        xRt <= 9'd0;
Line 90... Line 92...
        `BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
        `BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
                                xRt <= 9'd0;
                                xRt <= 9'd0;
        default:        xRt <= {dAXC,dIR[19:15]};
        default:        xRt <= {dAXC,dIR[19:15]};
        endcase
        endcase
end
end
 
        else
 
                xRt <= 9'd0;
 
end
else if (advanceX)
else if (advanceX)
        xRt <= 9'd0;
        xRt <= 9'd0;
end
end
 
 
endmodule
endmodule

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