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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_addsub.v] - Diff between revs 31 and 41

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Rev 31 Rev 41
Line 26... Line 26...
//                                                                          
//                                                                          
//
//
//=============================================================================
//=============================================================================
//
//
module Raptor64_addsub(xIR, a, b, imm, o);
module Raptor64_addsub(xIR, a, b, imm, o);
input [41:0] xIR;
input [31:0] xIR;
input [63:0] a;
input [63:0] a;
input [63:0] b;
input [63:0] b;
input [63:0] imm;
input [63:0] imm;
output [63:0] o;
output [63:0] o;
reg [63:0] o;
reg [63:0] o;
 
 
wire [6:0] xOpcode = xIR[41:35];
wire [6:0] xOpcode = xIR[31:25];
wire [6:0] xFunc = xIR[6:0];
wire [5:0] xFunc = xIR[5:0];
wire [7:0] bcdaddo,bcdsubo;
wire [7:0] bcdaddo,bcdsubo;
 
 
BCDAdd u1(.ci(1'b0),.a(a[7:0]),.b(b[7:0]),.o(bcdaddo),.c());
BCDAdd u1(.ci(1'b0),.a(a[7:0]),.b(b[7:0]),.o(bcdaddo),.c());
BCDSub u2(.ci(1'b0),.a(a[7:0]),.b(b[7:0]),.o(bcdsubo),.c());
BCDSub u2(.ci(1'b0),.a(a[7:0]),.b(b[7:0]),.o(bcdsubo),.c());
 
 

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