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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_addsub.v] - Diff between revs 31 and 41
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Rev 41 |
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//
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//
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//
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//
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//=============================================================================
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//=============================================================================
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//
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//
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module Raptor64_addsub(xIR, a, b, imm, o);
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module Raptor64_addsub(xIR, a, b, imm, o);
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input [41:0] xIR;
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input [31:0] xIR;
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input [63:0] a;
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input [63:0] a;
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input [63:0] b;
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input [63:0] b;
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input [63:0] imm;
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input [63:0] imm;
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output [63:0] o;
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output [63:0] o;
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reg [63:0] o;
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reg [63:0] o;
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wire [6:0] xOpcode = xIR[41:35];
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wire [6:0] xOpcode = xIR[31:25];
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wire [6:0] xFunc = xIR[6:0];
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wire [5:0] xFunc = xIR[5:0];
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wire [7:0] bcdaddo,bcdsubo;
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wire [7:0] bcdaddo,bcdsubo;
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BCDAdd u1(.ci(1'b0),.a(a[7:0]),.b(b[7:0]),.o(bcdaddo),.c());
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BCDAdd u1(.ci(1'b0),.a(a[7:0]),.b(b[7:0]),.o(bcdaddo),.c());
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BCDSub u2(.ci(1'b0),.a(a[7:0]),.b(b[7:0]),.o(bcdsubo),.c());
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BCDSub u2(.ci(1'b0),.a(a[7:0]),.b(b[7:0]),.o(bcdsubo),.c());
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