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https://opencores.org/ocsvn/raptor64/raptor64/trunk
[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_regfile.v] - Diff between revs 45 and 48
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Rev 45 |
Rev 48 |
Line 79... |
Line 79... |
.radrc(dRc),
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.radrc(dRc),
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.roc(rfoc)
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.roc(rfoc)
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);
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);
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reg [63:0] nxt_a;
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// casex(dRa)
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always @(dRa or xData or m1Data or m2Data or wData or tData or rfoa or dpc or xRt or m1Rt or m2Rt or wRt or tRt)
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// 9'bxxxx00000: nxt_a <= 64'd0;
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casex(dRa)
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// 9'bxxxx11101: nxt_a <= dpc;
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9'bxxxx00000: nxt_a <= 64'd0;
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// xRt: nxt_a <= xData;
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9'bxxxx11101: nxt_a <= dpc;
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// m1Rt: nxt_a <= m1Data;
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xRt: nxt_a <= xData;
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// m2Rt: nxt_a <= m2Data;
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m1Rt: nxt_a <= m1Data;
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// wRt: nxt_a <= wData;
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m2Rt: nxt_a <= m2Data;
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// tRt: nxt_a <= tData;
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wRt: nxt_a <= wData;
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// default: nxt_a <= rfoa;
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tRt: nxt_a <= tData;
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// endcase
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default: nxt_a <= rfoa;
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endcase
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//reg [63:0] nxt_b;
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//always @(dRb or xData or m1Data or m2Data or wData or tData or rfob or dpc or xRt or m1Rt or m2Rt or wRt or tRt)
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reg [63:0] nxt_b;
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// casex(dRb)
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always @(dRb or xData or m1Data or m2Data or wData or tData or rfob or dpc or xRt or m1Rt or m2Rt or wRt or tRt)
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// 9'bxxxx00000: nxt_b <= 64'd0;
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casex(dRb)
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// 9'bxxxx11101: nxt_b <= dpc;
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9'bxxxx00000: nxt_b <= 64'd0;
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// xRt: nxt_b <= xData;
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9'bxxxx11101: nxt_b <= dpc;
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// m1Rt: nxt_b <= m1Data;
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xRt: nxt_b <= xData;
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// m2Rt: nxt_b <= m2Data;
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m1Rt: nxt_b <= m1Data;
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// wRt: nxt_b <= wData;
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m2Rt: nxt_b <= m2Data;
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// tRt: nxt_b <= tData;
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wRt: nxt_b <= wData;
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// default: nxt_b <= rfob;
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tRt: nxt_b <= tData;
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// endcase
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default: nxt_b <= rfob;
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//
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endcase
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//reg [63:0] nxt_c;
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//always @(dRc or xData or m1Data or m2Data or wData or tData or rfoc or dpc or xRt or m1Rt or m2Rt or wRt or tRt)
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reg [63:0] nxt_c;
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// casex(dRc)
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always @(dRc or xData or m1Data or m2Data or wData or tData or rfoc or dpc or xRt or m1Rt or m2Rt or wRt or tRt)
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// 9'bxxxx00000: nxt_c <= 64'd0;
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casex(dRc)
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// 9'bxxxx11101: nxt_c <= dpc;
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9'bxxxx00000: nxt_c <= 64'd0;
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// xRt: nxt_c <= xData;
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9'bxxxx11101: nxt_c <= dpc;
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// m1Rt: nxt_c <= m1Data;
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xRt: nxt_c <= xData;
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// m2Rt: nxt_c <= m2Data;
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m1Rt: nxt_c <= m1Data;
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// wRt: nxt_c <= wData;
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m2Rt: nxt_c <= m2Data;
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// tRt: nxt_c <= tData;
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wRt: nxt_c <= wData;
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// default: nxt_c <= rfoc;
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tRt: nxt_c <= tData;
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// endcase
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default: nxt_c <= rfoc;
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endcase
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endmodule
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endmodule
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