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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_set.v] - Diff between revs 31 and 41
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| Rev 31 |
Rev 41 |
| Line 26... |
Line 26... |
//
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//
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//
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//
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//=============================================================================
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//=============================================================================
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//
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//
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module Raptor64_set(xIR, a, b, imm, o);
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module Raptor64_set(xIR, a, b, imm, o);
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input [41:0] xIR;
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input [31:0] xIR;
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input [63:0] a;
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input [63:0] a;
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input [63:0] b;
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input [63:0] b;
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input [63:0] imm;
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input [63:0] imm;
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output [63:0] o;
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output [63:0] o;
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reg [63:0] o;
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reg [63:0] o;
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wire [6:0] xOpcode = xIR[41:35];
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wire [6:0] xOpcode = xIR[31:25];
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wire [6:0] xFunc = xIR[6:0];
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wire [5:0] xFunc = xIR[5:0];
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wire eqi = a==imm;
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wire eqi = a==imm;
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wire lti = $signed(a) < $signed(imm);
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wire lti = $signed(a) < $signed(imm);
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wire ltui = a < imm;
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wire ltui = a < imm;
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wire eq = a==b;
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wire eq = a==b;
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