| Line 30... |
Line 30... |
wire tc_ack;
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wire tc_ack;
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wire pic_ack;
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wire pic_ack;
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reg pulse1000Hz,pulse100Hz;
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reg pulse1000Hz,pulse100Hz;
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wire [7:0] config_rec;
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wire [7:0] config_rec;
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reg [7:0] config_reco;
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reg [7:0] config_reco;
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//wire sm_ack;
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wire [7:0] sm_dato;
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wire uart_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC_0A);
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wire uart_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC_0A);
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wire rast_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDA_01);
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wire rast_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDA_01);
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wire AC97_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC_10);
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wire AC97_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC_10);
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wire spr_ack = sys_iocyc && sys_stb && (sys_adr[23:16]==8'hD8);
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wire spr_ack = sys_iocyc && sys_stb && (sys_adr[23:16]==8'hD8);
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wire Led_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC_06);
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wire Led_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC_06);
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wire dt_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC_04);
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wire dt_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC_04);
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wire p100ack = sys_iocyc && sys_stb && (sys_adr[23:0]==24'hDCFFFC);
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wire p100ack = sys_iocyc && sys_stb && (sys_adr[23:0]==24'hDCFFFC);
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wire p1000ack = sys_iocyc && sys_stb && (sys_adr[23:0]==24'hDCFFFD);
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wire p1000ack = sys_iocyc && sys_stb && (sys_adr[23:0]==24'hDCFFFD);
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wire config_rec_ack = sys_iocyc && sys_stb && sys_adr[23:0]==24'hDCFFFF;
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wire config_rec_ack = sys_iocyc && sys_stb && sys_adr[23:3]==21'b1101_1100_1111_1111_1111_0;
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wire perr_ack = sys_iocyc && sys_stb && sys_adr[23:0]==24'hDCFFFE;
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wire perr_ack = sys_iocyc && sys_stb && sys_adr[23:0]==24'hDCFFFE;
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wire tmp_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC03);
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wire tmp_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC03);
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wire sm_ack = sys_iocyc && sys_stb && (sys_adr[23:16]==8'hDB);
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assign ram_ack = sys_cyc && sys_stb && (sys_adr[63:32]==32'd1);
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//assign ram_ack = sys_cyc && sys_stb && (sys_adr[63:32]==32'd1);
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assign sys_ack = br_ack|stk_ack|scr_ack|tc_ack|pic_ack|ram_ack|uart_ack|rast_ack|AC97_ack|spr_ack|Led_ack|dt_ack|p100ack|p1000ack|config_rec_ack|tmp_ack|perr_ack;
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assign config_rec = 8'b0000_0111;
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assign config_rec = 8'b0000_0111;
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always @(config_rec_ack)
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always @(config_rec_ack)
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config_reco <= config_rec_ack ? config_rec : 8'd0;
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config_reco <= config_rec_ack ? config_rec : 8'd0;
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wire cs_ram = sys_cyc && sys_stb && (sys_adr[63:32]==32'd1);
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reg [63:0] sysram [0:16000];
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always @(posedge clk)
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if (cs_ram & sys_we) begin
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$display("Wrote ram[%h]=%h", sys_adr, sys_dbo);
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sysram[sys_adr[15:3]] <= sys_dbo;
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end
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wire [63:0] ramo = cs_ram ? sysram[sys_adr[15:3]] : 64'd0;
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reg ack1,ack2,ack3,ack4,ack5,ack6,ack7,ack8;
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always @(posedge clk)
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begin
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ack1 <= cs_ram;
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ack2 <= ack1 & cs_ram;
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ack3 <= ack2 & cs_ram;
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ack4 <= ack3 & cs_ram;
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ack5 <= ack4 & cs_ram;
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ack6 <= ack5 & cs_ram;
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ack7 <= ack6 & cs_ram;
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ack8 <= ack7 & cs_ram;
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end
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wire ram_ack = cs_ram & ack8;
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assign sys_ack = br_ack|stk_ack|scr_ack|tc_ack|pic_ack|ram_ack|uart_ack|rast_ack|
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AC97_ack|spr_ack|Led_ack|dt_ack|
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p100ack|p1000ack|config_rec_ack|tmp_ack|perr_ack|sm_ack;
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initial begin
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initial begin
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clk = 1;
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clk = 1;
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pulse1000Hz = 0;
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pulse1000Hz = 0;
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pulse100Hz = 0;
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pulse100Hz = 0;
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| Line 92... |
Line 119... |
if (p100ack)
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if (p100ack)
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pulse100HzB <= 1'b0;
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pulse100HzB <= 1'b0;
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end
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end
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end
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end
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//sema_mem usm
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//(
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// .rst_i(rst),
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// .clk_i(clk),
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// .cyc_i(sys_iocyc),
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// .stb_i(sys_stb),
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// .ack_o(sm_ack),
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// .we_i(sys_we),
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// .adr_i(sys_adr[23:0]),
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// .dat_i(sys_dbo[7:0]),
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// .dat_o(sm_dato)
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//);
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rtfTextController tc1
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rtfTextController tc1
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(
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(
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.rst_i(rst),
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.rst_i(rst),
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.clk_i(clk),
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.clk_i(clk),
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| Line 828... |
Line 868... |
64'hFFFFFFFFFFFFFFE8: romout <= 64'h37800000000DE000;
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64'hFFFFFFFFFFFFFFE8: romout <= 64'h37800000000DE000;
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64'hFFFFFFFFFFFFFFF0: romout <= 64'h000000CFFFFFFA00;
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64'hFFFFFFFFFFFFFFF0: romout <= 64'h000000CFFFFFFA00;
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64'hFFFFFFFFFFFFFFF8: romout <= 64'h37800000000DE000;
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64'hFFFFFFFFFFFFFFF8: romout <= 64'h37800000000DE000;
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default: romout <= 64'd0;
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default: romout <= 64'd0;
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endcase
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endcase
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assign sys_dbi = br_dato|keybdout|stk_dato|scr_dato| {4{tc_dato}} | {4{pic_dato}} | {8{config_reco}};
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assign sys_dbi = br_dato|keybdout|stk_dato|scr_dato| {4{tc_dato}}
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| {4{pic_dato}} | {8{config_reco}} | ramo | {8{sm_dato}};
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Raptor64sc u1
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Raptor64sc u1
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(
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(
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.rst_i(rst),
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.rst_i(rst),
|
