| Line 27... |
Line 27... |
wire [63:0] scr_dato;
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wire [63:0] scr_dato;
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wire [15:0] tc_dato;
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wire [15:0] tc_dato;
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wire [15:0] pic_dato;
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wire [15:0] pic_dato;
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wire tc_ack;
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wire tc_ack;
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wire pic_ack;
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wire pic_ack;
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reg pulse1000Hz;
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reg pulse1000Hz,pulse100Hz;
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wire uart_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC_0A);
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wire uart_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC_0A);
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wire rast_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDA_01);
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wire rast_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDA_01);
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wire AC97_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC_10);
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wire AC97_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC_10);
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wire spr_ack = sys_iocyc && sys_stb && (sys_adr[23:16]==8'hD8);
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wire spr_ack = sys_iocyc && sys_stb && (sys_adr[23:16]==8'hD8);
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wire Led_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC_06);
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wire Led_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC_06);
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wire dt_ack = sys_iocyc && sys_stb && (sys_adr[23:8]==16'hDC_04);
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wire p100ack = sys_iocyc && sys_stb && (sys_adr[63:0]==64'hFFFFFFFF_FFFF0010);
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wire p1000ack = sys_iocyc && sys_stb && (sys_adr[63:0]==64'hFFFFFFFF_FFFF0000);
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assign ram_ack = sys_cyc && sys_stb && (sys_adr[63:32]==32'd1);
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assign ram_ack = sys_cyc && sys_stb && (sys_adr[63:32]==32'd1);
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assign sys_ack = br_ack|stk_ack|scr_ack|tc_ack|pic_ack|ram_ack|uart_ack|rast_ack|AC97_ack|spr_ack|Led_ack;
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assign sys_ack = br_ack|stk_ack|scr_ack|tc_ack|pic_ack|ram_ack|uart_ack|rast_ack|AC97_ack|spr_ack|Led_ack|dt_ack|p100ack|p1000ack;
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initial begin
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initial begin
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clk = 1;
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clk = 1;
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pulse1000Hz = 0;
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pulse1000Hz = 0;
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pulse100Hz = 0;
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rst = 0;
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rst = 0;
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nmi = 0;
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nmi = 0;
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#100 rst = 1;
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#100 rst = 1;
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#100 rst = 0;
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#100 rst = 0;
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#800 nmi = 1;
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#800 nmi = 1;
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#100 nmi = 0;
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#100 nmi = 0;
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end
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end
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always #10 clk = ~clk; // 50 MHz
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always #20 clk = ~clk; // 25 MHz
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always #290930 pulse1000Hz = 1;
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always #29930 pulse1000Hz = 1;
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always #130 pulse1000Hz = 0;
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always #130 pulse1000Hz = 0;
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always #299030 pulse100Hz = 1;
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always #130 pulse100Hz = 0;
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reg pulse1000HzB;
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reg pulse1000HzB,pulse100HzB;
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always @(posedge clk)
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always @(posedge clk)
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if (rst) begin
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if (rst) begin
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pulse1000HzB <= 1'b0;
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pulse1000HzB <= 1'b0;
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pulse100HzB <= 1'b0;
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end
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end
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else begin
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else begin
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if (pulse1000Hz)
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if (pulse1000Hz)
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pulse1000HzB <= 1'b1;
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pulse1000HzB <= 1'b1;
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else begin
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else begin
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if (sys_adr==64'hFFFFFFFF_FFFF0000)
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if (p1000ack)
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pulse1000HzB <= 1'b0;
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pulse1000HzB <= 1'b0;
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end
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end
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if (pulse100Hz)
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pulse100HzB <= 1'b1;
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else begin
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if (p100ack)
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pulse100HzB <= 1'b0;
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end
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end
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end
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rtfTextController tc1
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rtfTextController tc1
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(
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(
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| Line 143... |
Line 156... |
.dat_i(sys_dbo[15:0]),
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.dat_i(sys_dbo[15:0]),
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.dat_o(pic_dato),
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.dat_o(pic_dato),
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.vol_o(), // volatile register selected
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.vol_o(), // volatile register selected
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.i1(),
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.i1(),
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.i2(pulse1000HzB),
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.i2(pulse1000HzB),
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.i3(), .i4(), .i5(), .i6(), .i7(),
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.i3(pulse100HzB),
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.i4(), .i5(), .i6(), .i7(),
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.i8(), .i9(), .i10(), .i11(), .i12(), .i13(), .i14(),
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.i8(), .i9(), .i10(), .i11(), .i12(), .i13(), .i14(),
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.i15(),
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.i15(),
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.irqo(cpu_irq), // normally connected to the processor irq
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.irqo(cpu_irq), // normally connected to the processor irq
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.nmii(nmi), // nmi input connected to nmi requester
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.nmii(nmi), // nmi input connected to nmi requester
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.nmio(cpu_nmi), // normally connected to the nmi of cpu
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.nmio(cpu_nmi), // normally connected to the nmi of cpu
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