| Line 414... |
Line 414... |
reg [41:0] dIR;
|
reg [41:0] dIR;
|
reg [41:0] xIR;
|
reg [41:0] xIR;
|
reg [63:0] pc;
|
reg [63:0] pc;
|
reg [63:0] ErrorEPC,EPC,IPC;
|
reg [63:0] ErrorEPC,EPC,IPC;
|
reg [63:0] dpc,m1pc,m2pc,m3pc,m4pc,wpc;
|
reg [63:0] dpc,m1pc,m2pc,m3pc,m4pc,wpc;
|
|
reg dpcv,xpcv,m1pcv,m2pcv,m3pcv,m4pcv,wpcv; // PC valid indicators
|
reg [63:0] xpc;
|
reg [63:0] xpc;
|
reg [63:0] tlbra; // return address for a TLB exception
|
reg [63:0] tlbra; // return address for a TLB exception
|
reg [8:0] dRa,dRb,dRc;
|
reg [8:0] dRa,dRb,dRc;
|
reg [8:0] wRt,mRt,m1Rt,m2Rt,m3Rt,m4Rt,tRt,dRt;
|
reg [8:0] wRt,mRt,m1Rt,m2Rt,m3Rt,m4Rt,tRt,dRt;
|
reg [8:0] xRt;
|
reg [8:0] xRt;
|
| Line 1112... |
Line 1113... |
lt or eq or ltu or mult_out or lti or eqi or ltui or xIR or div_q or div_r or
|
lt or eq or ltu or mult_out or lti or eqi or ltui or xIR or div_q or div_r or
|
shfto or masko or bcdaddo or bcdsubo or fpLooOut or fpZLOut or
|
shfto or masko or bcdaddo or bcdsubo or fpLooOut or fpZLOut or
|
Wired or Index or Random or TLBPhysPage0 or TLBPhysPage1 or TLBVirtPage or TLBASID or
|
Wired or Index or Random or TLBPhysPage0 or TLBPhysPage1 or TLBVirtPage or TLBASID or
|
PageTableAddr or BadVAddr or ASID or TLBPageMask
|
PageTableAddr or BadVAddr or ASID or TLBPageMask
|
)
|
)
|
case(xOpcode)
|
casex(xOpcode)
|
`R:
|
`R:
|
casex(xFunc)
|
casex(xFunc)
|
`SETLO: xData = imm;
|
|
`SETHI: xData = {imm[63:32],a[31:0]};
|
|
`COM: xData = ~a;
|
`COM: xData = ~a;
|
`NOT: xData = ~|a;
|
`NOT: xData = ~|a;
|
`NEG: xData = -a;
|
`NEG: xData = -a;
|
`ABS: xData = a[63] ? -a : a;
|
`ABS: xData = a[63] ? -a : a;
|
`SQRT: xData = sqrt_out;
|
`SQRT: xData = sqrt_out;
|
| Line 1499... |
Line 1498... |
m2Fip <= 1'b0;
|
m2Fip <= 1'b0;
|
m1Fip <= 1'b0;
|
m1Fip <= 1'b0;
|
xFip <= 1'b0;
|
xFip <= 1'b0;
|
dFip <= 1'b0;
|
dFip <= 1'b0;
|
dirqf <= 1'b0;
|
dirqf <= 1'b0;
|
|
dpcv <= 1'b0;
|
|
xpcv <= 1'b0;
|
|
m1pcv <= 1'b0;
|
|
m2pcv <= 1'b0;
|
|
wpcv <= 1'b0;
|
tick <= 32'd0;
|
tick <= 32'd0;
|
cstate <= IDLE;
|
cstate <= IDLE;
|
dImm <= 64'd0;
|
dImm <= 64'd0;
|
AXC <= 4'd0;
|
AXC <= 4'd0;
|
dAXC <= 4'd0;
|
dAXC <= 4'd0;
|
| Line 1577... |
Line 1581... |
if (advanceW) begin
|
if (advanceW) begin
|
textype <= wextype;
|
textype <= wextype;
|
wextype <= `EX_NON;
|
wextype <= `EX_NON;
|
tRt <= wRt;
|
tRt <= wRt;
|
tData <= wData;
|
tData <= wData;
|
// regfile[wRt] <= wData; <- regfile.v
|
if (wRt!=5'd0)
|
$display("Writing regfile[%d:%d] with %h", wRt[8:5],wRt[4:0], wData);
|
$display("Writing regfile[%d:%d] with %h", wRt[8:5],wRt[4:0], wData);
|
wRt <= 9'd0;
|
wRt <= 9'd0;
|
wData <= 64'd0;
|
wData <= 64'd0;
|
if (|whwxtype) begin
|
if (|whwxtype) begin
|
dhwxtype <= 2'b00;
|
dhwxtype <= 2'b00;
|
| Line 1618... |
Line 1622... |
wData <= m2Data;
|
wData <= m2Data;
|
whwxtype <= m2hwxtype;
|
whwxtype <= m2hwxtype;
|
wextype <= m2extype;
|
wextype <= m2extype;
|
wRt <= m2Rt;
|
wRt <= m2Rt;
|
wpc <= m2pc;
|
wpc <= m2pc;
|
|
wpcv <= m2pcv;
|
wclkoff <= m2clkoff;
|
wclkoff <= m2clkoff;
|
wFip <= m2Fip;
|
wFip <= m2Fip;
|
|
|
m2Rt <= 9'd0;
|
m2Rt <= 9'd0;
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
| Line 1752... |
Line 1757... |
m2Data <= m1Data;
|
m2Data <= m1Data;
|
m2hwxtype <= m1hwxtype;
|
m2hwxtype <= m1hwxtype;
|
m2extype <= m1extype;
|
m2extype <= m1extype;
|
m2Rt <= m1Rt;
|
m2Rt <= m1Rt;
|
m2pc <= m1pc;
|
m2pc <= m1pc;
|
|
m2pcv <= m1pcv;
|
m2clkoff <= m1clkoff;
|
m2clkoff <= m1clkoff;
|
m2Fip <= m1Fip;
|
m2Fip <= m1Fip;
|
|
|
m1Rt <= 9'd0;
|
m1Rt <= 9'd0;
|
m1Opcode <= `NOPI;
|
m1Opcode <= `NOPI;
|
| Line 2189... |
Line 2195... |
if (xOpcode==`MOVNZ && aeqz) begin
|
if (xOpcode==`MOVNZ && aeqz) begin
|
m1Rt <= 9'd0;
|
m1Rt <= 9'd0;
|
m1Data <= 64'd0;
|
m1Data <= 64'd0;
|
end
|
end
|
m1pc <= xpc;
|
m1pc <= xpc;
|
|
m1pcv <= xpcv;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
a <= 64'd0;
|
a <= 64'd0;
|
b <= 64'd0;
|
b <= 64'd0;
|
imm <= 64'd0;
|
imm <= 64'd0;
|
xextype <= `EX_NON;
|
xextype <= `EX_NON;
|
| Line 2372... |
Line 2379... |
xhwxtype <= dhwxtype;
|
xhwxtype <= dhwxtype;
|
xFip <= dFip;
|
xFip <= dFip;
|
xextype <= dextype;
|
xextype <= dextype;
|
xIR <= dIR;
|
xIR <= dIR;
|
xpc <= dpc;
|
xpc <= dpc;
|
|
xpcv <= dpcv;
|
xbranch_taken <= dbranch_taken;
|
xbranch_taken <= dbranch_taken;
|
dbranch_taken <= 1'b0;
|
dbranch_taken <= 1'b0;
|
dextype <= `EX_NON;
|
dextype <= `EX_NON;
|
if (dOpcode[6:4]!=`IMM) // IMM is "sticky"
|
if (dOpcode[6:4]!=`IMM) // IMM is "sticky"
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
| Line 2488... |
Line 2496... |
StatusHWI <= 1'b1;
|
StatusHWI <= 1'b1;
|
nmi_edge <= 1'b0;
|
nmi_edge <= 1'b0;
|
dhwxtype <= 2'b01;
|
dhwxtype <= 2'b01;
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
dextype <= `EX_NMI;
|
dextype <= `EX_NMI;
|
IPC <= pc;
|
|
end
|
end
|
else if (irq_i & !im & !StatusHWI) begin
|
else if (irq_i & !im & !StatusHWI) begin
|
|
im <= 1'b1;
|
StatusHWI <= 1'b1;
|
StatusHWI <= 1'b1;
|
dhwxtype <= 2'b10;
|
dhwxtype <= 2'b10;
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
dextype <= `EX_IRQ;
|
dextype <= `EX_IRQ;
|
IPC <= pc;
|
|
end
|
end
|
// Are we filling the pipeline with NOP's as a result of a previous
|
// Are we filling the pipeline with NOP's as a result of a previous
|
// hardware interrupt ?
|
// hardware interrupt ?
|
else if (|dhwxtype|dFip) begin
|
else if (|dhwxtype|dFip) begin
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
| Line 2511... |
Line 2518... |
`include "insn_dumpsc.v"
|
`include "insn_dumpsc.v"
|
end
|
end
|
nopI <= 1'b0;
|
nopI <= 1'b0;
|
if (dOpcode[6:4]!=`IMM) begin
|
if (dOpcode[6:4]!=`IMM) begin
|
dpc <= pc;
|
dpc <= pc;
|
|
dpcv <= 1'b1;
|
end
|
end
|
casex(iOpcode)
|
casex(iOpcode)
|
`SETLO: dRa <= {AXC,insn[36:32]};
|
`SETLO: dRa <= {AXC,insn[36:32]};
|
`SETHI: dRa <= {AXC,insn[36:32]};
|
`SETHI: dRa <= {AXC,insn[36:32]};
|
default: dRa <= {AXC,insn[34:30]};
|
default: dRa <= {AXC,insn[34:30]};
|
| Line 2580... |
Line 2588... |
`MISC:
|
`MISC:
|
case(xFunc)
|
case(xFunc)
|
`IRET:
|
`IRET:
|
if (StatusHWI) begin
|
if (StatusHWI) begin
|
StatusHWI <= 1'b0;
|
StatusHWI <= 1'b0;
|
|
im <= 1'b0;
|
pc <= IPC;
|
pc <= IPC;
|
dpc <= IPC;
|
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xpc <= IPC;
|
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
|
xpcv <= 1'b0;
|
|
dpcv <= 1'b0;
|
end
|
end
|
`ERET:
|
`ERET:
|
if (StatusEXL) begin
|
if (StatusEXL) begin
|
StatusEXL <= 1'b0;
|
StatusEXL <= 1'b0;
|
pc <= EPC;
|
pc <= EPC;
|
dpc <= EPC;
|
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xpc <= EPC;
|
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
|
xpcv <= 1'b0;
|
|
dpcv <= 1'b0;
|
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
`BTRR:
|
`BTRR:
|
case(xIR[4:0])
|
case(xIR[4:0])
|
// BEQ r1,r2,label
|
// BEQ r1,r2,label
|
`BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BAND,`BOR,`BNR:
|
`BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BAND,`BOR,`BNR:
|
if (!takb & xbranch_taken) begin
|
if (!takb & xbranch_taken) begin
|
$display("Taking mispredicted branch %h",fnIncPC(xpc));
|
$display("Taking mispredicted branch %h",fnIncPC(xpc));
|
pc <= fnIncPC(xpc);
|
pc <= fnIncPC(xpc);
|
dpc <= fnIncPC(xpc);
|
|
xpc <= fnIncPC(xpc);
|
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
|
xpcv <= 1'b0;
|
|
dpcv <= 1'b0;
|
end
|
end
|
else if (takb & !xbranch_taken) begin
|
else if (takb & !xbranch_taken) begin
|
$display("Taking branch %h.%h",{xpc[63:4] + {{42{xIR[24]}},xIR[24:7]},4'b0000},xIR[6:5]);
|
$display("Taking branch %h.%h",{xpc[63:4] + {{42{xIR[24]}},xIR[24:7]},4'b0000},xIR[6:5]);
|
pc[63:4] <= xpc[63:4] + {{42{xIR[24]}},xIR[24:7]};
|
pc[63:4] <= xpc[63:4] + {{42{xIR[24]}},xIR[24:7]};
|
pc[3:2] <= xIR[6:5];
|
pc[3:2] <= xIR[6:5];
|
dpc[63:4] <= xpc[63:4] + {{42{xIR[24]}},xIR[24:7]};
|
|
dpc[3:2] <= xIR[6:5];
|
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xpc[63:4] <= xpc[63:4] + {{42{xIR[24]}},xIR[24:7]};
|
|
xpc[3:2] <= xIR[6:5];
|
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
|
xpcv <= 1'b0;
|
|
dpcv <= 1'b0;
|
end
|
end
|
// BEQ r1,r2,r10
|
// BEQ r1,r2,r10
|
`BEQR,`BNER,`BLTR,`BLER,`BGTR,`BGER,`BLTUR,`BLEUR,`BGTUR,`BGEUR://,`BANDR,`BORR,`BNRR:
|
`BEQR,`BNER,`BLTR,`BLER,`BGTR,`BGER,`BLTUR,`BLEUR,`BGTUR,`BGEUR://,`BANDR,`BORR,`BNRR:
|
if (takb) begin
|
if (takb) begin
|
pc[63:2] <= c[63:2];
|
pc[63:2] <= c[63:2];
|
pc[1:0] <= 2'b00;
|
pc[1:0] <= 2'b00;
|
dpc[63:2] <= c[63:2];
|
|
dpc[1:0] <= 2'b00;
|
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xpc[63:2] <= c[63:2];
|
|
xpc[1:0] <= 2'b00;
|
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
|
xpcv <= 1'b0;
|
|
dpcv <= 1'b0;
|
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
// JMP and CALL change the program counter immediately in the IF stage.
|
// JMP and CALL change the program counter immediately in the IF stage.
|
// There's no work to do here. The pipeline does not need to be cleared.
|
// There's no work to do here. The pipeline does not need to be cleared.
|
| Line 2647... |
Line 2652... |
`CALL: ;
|
`CALL: ;
|
`JAL:
|
`JAL:
|
begin
|
begin
|
pc[63:2] <= a[63:2] + imm[63:2];
|
pc[63:2] <= a[63:2] + imm[63:2];
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
dpc[63:2] <= a[63:2] + imm[63:2];
|
|
xpc[63:2] <= a[63:2] + imm[63:2];
|
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
|
xpcv <= 1'b0;
|
|
dpcv <= 1'b0;
|
end
|
end
|
`RET:
|
`RET:
|
begin
|
begin
|
$display("returning to: %h", {b,2'b00});
|
$display("returning to: %h", {b,2'b00});
|
pc[63:2] <= b[63:2];
|
pc[63:2] <= b[63:2];
|
dpc[63:2] <= b[63:2];
|
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xpc[63:2] <= b[63:2];
|
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
|
xpcv <= 1'b0;
|
|
dpcv <= 1'b0;
|
end
|
end
|
// BEQ r1,#3,r10
|
// BEQ r1,#3,r10
|
`BTRI:
|
`BTRI:
|
if (takb) begin
|
if (takb) begin
|
pc[63:2] <= b[63:2];
|
pc[63:2] <= b[63:2];
|
pc[1:0] <= 2'b00;
|
pc[1:0] <= 2'b00;
|
dpc[63:2] <= b[63:2];
|
|
dpc[1:0] <= 2'b00;
|
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xpc[63:2] <= b[63:2];
|
|
xpc[1:0] <= 2'b00;
|
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
|
xpcv <= 1'b0;
|
|
dpcv <= 1'b0;
|
end
|
end
|
// BEQI r1,#3,label
|
// BEQI r1,#3,label
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
if (takb) begin
|
if (takb) begin
|
if (!xbranch_taken) begin
|
if (!xbranch_taken) begin
|
pc[63:4] <= xpc[63:4] + {{50{xIR[29]}},xIR[29:20]};
|
pc[63:4] <= xpc[63:4] + {{50{xIR[29]}},xIR[29:20]};
|
pc[3:2] <= xIR[19:18];
|
pc[3:2] <= xIR[19:18];
|
dpc[63:4] <= xpc[63:4] + {{50{xIR[29]}},xIR[29:20]};
|
|
dpc[3:2] <= xIR[19:18];
|
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xpc[63:4] <= xpc[63:4] + {{50{xIR[29]}},xIR[29:20]};
|
|
xpc[3:2] <= xIR[19:18];
|
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
|
xpcv <= 1'b0;
|
|
dpcv <= 1'b0;
|
end
|
end
|
end
|
end
|
else begin
|
else begin
|
if (xbranch_taken) begin
|
if (xbranch_taken) begin
|
$display("Taking mispredicted branch %h",fnIncPC(xpc));
|
$display("Taking mispredicted branch %h",fnIncPC(xpc));
|
pc <= fnIncPC(xpc);
|
pc <= fnIncPC(xpc);
|
dpc <= fnIncPC(xpc);
|
|
xpc <= fnIncPC(xpc);
|
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
|
xpcv <= 1'b0;
|
|
dpcv <= 1'b0;
|
end
|
end
|
end
|
end
|
`TRAPcc,`TRAPcci:
|
`TRAPcc,`TRAPcci:
|
if (takb) begin
|
if (takb) begin
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
CauseCode <= `EX_TRAP;
|
CauseCode <= `EX_TRAP;
|
EPC <= xpc;
|
EPC <= xpc;
|
if (!xbranch_taken) begin
|
if (!xbranch_taken) begin
|
pc <= {TBA[63:13],`GEN_TRAP_OFFSET};
|
pc <= {TBA[63:13],`GEN_TRAP_OFFSET};
|
dpc <= {TBA[63:13],`GEN_TRAP_OFFSET};
|
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xpc <= {TBA[63:13],`GEN_TRAP_OFFSET};
|
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
|
xpcv <= 1'b0;
|
|
dpcv <= 1'b0;
|
end
|
end
|
end
|
end
|
else begin
|
else begin
|
if (xbranch_taken) begin
|
if (xbranch_taken) begin
|
$display("Taking mispredicted branch %h",fnIncPC(xpc));
|
$display("Taking mispredicted branch %h",fnIncPC(xpc));
|
pc <= fnIncPC(xpc);
|
pc <= fnIncPC(xpc);
|
dpc <= fnIncPC(xpc);
|
|
xpc <= fnIncPC(xpc);
|
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
|
xpcv <= 1'b0;
|
|
dpcv <= 1'b0;
|
end
|
end
|
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
|
|
| Line 2735... |
Line 2736... |
$display("Divide by zero error");
|
$display("Divide by zero error");
|
CauseCode <= `EX_DBZ;
|
CauseCode <= `EX_DBZ;
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
EPC <= xpc;
|
EPC <= xpc;
|
pc <= {TBA[63:13],`DBZ_TRAP_OFFSET};
|
pc <= {TBA[63:13],`DBZ_TRAP_OFFSET};
|
dpc <= {TBA[63:13],`DBZ_TRAP_OFFSET};
|
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xpc <= {TBA[63:13],`DBZ_TRAP_OFFSET};
|
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
|
xpcv <= 1'b0;
|
|
dpcv <= 1'b0;
|
end
|
end
|
else if (ovr_error) begin
|
else if (ovr_error) begin
|
$display("Overflow error");
|
$display("Overflow error");
|
CauseCode <= `EX_OFL;
|
CauseCode <= `EX_OFL;
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
EPC <= xpc;
|
EPC <= xpc;
|
pc <= {TBA[63:13],`OFL_TRAP_OFFSET};
|
pc <= {TBA[63:13],`OFL_TRAP_OFFSET};
|
dpc <= {TBA[63:13],`OFL_TRAP_OFFSET};
|
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xpc <= {TBA[63:13],`OFL_TRAP_OFFSET};
|
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
|
xpcv <= 1'b0;
|
|
dpcv <= 1'b0;
|
end
|
end
|
else if (priv_violation) begin
|
else if (priv_violation) begin
|
$display("Priviledge violation");
|
$display("Priviledge violation");
|
CauseCode <= `EX_PRIV;
|
CauseCode <= `EX_PRIV;
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
EPC <= xpc;
|
EPC <= xpc;
|
pc <= {TBA[63:13],`PRIV_OFFSET};
|
pc <= {TBA[63:13],`PRIV_OFFSET};
|
dpc <= {TBA[63:13],`PRIV_OFFSET};
|
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xpc <= {TBA[63:13],`PRIV_OFFSET};
|
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
|
xpcv <= 1'b0;
|
|
dpcv <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// MEMORY1 (M1') - part two:
|
// MEMORY1 (M1') - part two:
|
| Line 2781... |
Line 2782... |
CauseCode <= `EX_TLBD;
|
CauseCode <= `EX_TLBD;
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
BadVAddr <= ea[63:13];
|
BadVAddr <= ea[63:13];
|
EPC <= m1pc;
|
EPC <= m1pc;
|
pc <= `DTLB_MissHandler;
|
pc <= `DTLB_MissHandler;
|
m1pc <= `DTLB_MissHandler;
|
|
m1Opcode <= `NOPI;
|
m1Opcode <= `NOPI;
|
m1Rt <= 9'd0;
|
m1Rt <= 9'd0;
|
xpc <= `DTLB_MissHandler;
|
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
dpc <= `DTLB_MissHandler;
|
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
|
m1pcv <= 1'b0;
|
|
xpcv <= 1'b0;
|
|
dpcv <= 1'b0;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
| Line 2809... |
Line 2810... |
// NOP instructions. This means there is no need to
|
// NOP instructions. This means there is no need to
|
// invalidate the pipeline.
|
// invalidate the pipeline.
|
// Also, we have to wait until the WB stage before
|
// Also, we have to wait until the WB stage before
|
// vectoring so that the pc setting doesn't get trashed
|
// vectoring so that the pc setting doesn't get trashed
|
// by a branch or other exception.
|
// by a branch or other exception.
|
|
// Tricky because we have to find the first valid
|
|
// PC to record in the IPC register. The interrupt might
|
|
// have occurred in a branch shadow, in which case the
|
|
// current PC isn't valid.
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (advanceW) begin
|
if (advanceW) begin
|
case(wextype)
|
case(wextype)
|
`EX_RST: pc <= `RESET_VECTOR;
|
`EX_RST: begin
|
`EX_NMI: pc <= `NMI_VECTOR;
|
pc <= `RESET_VECTOR;
|
`EX_IRQ: pc <= `IRQ_VECTOR;
|
case(1'b1)
|
|
wpcv: IPC <= wpc;
|
|
m2pcv: IPC <= m2pc;
|
|
m1pcv: IPC <= m1pc;
|
|
xpcv: IPC <= xpc;
|
|
dpcv: IPC <= dpc;
|
|
default: IPC <= pc;
|
|
endcase
|
|
end
|
|
`EX_NMI: begin
|
|
pc <= `NMI_VECTOR;
|
|
case(1'b1)
|
|
wpcv: IPC <= wpc;
|
|
m2pcv: IPC <= m2pc;
|
|
m1pcv: IPC <= m1pc;
|
|
xpcv: IPC <= xpc;
|
|
dpcv: IPC <= dpc;
|
|
default: IPC <= pc;
|
|
endcase
|
|
end
|
|
`EX_IRQ: begin
|
|
pc <= `IRQ_VECTOR;
|
|
case(1'b1)
|
|
wpcv: IPC <= wpc;
|
|
m2pcv: IPC <= m2pc;
|
|
m1pcv: IPC <= m1pc;
|
|
xpcv: IPC <= xpc;
|
|
dpcv: IPC <= dpc;
|
|
default: IPC <= pc;
|
|
endcase
|
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
