Subversion Repositories raptor64

// You should have received a copy of the GNU General Public License        

// You should have received a copy of the GNU General Public License        

// along with this program.  If not, see <http://www.gnu.org/licenses/>.    

// along with this program.  If not, see <http://www.gnu.org/licenses/>.    

//                                                                          

//                                                                          

// ============================================================================

// ============================================================================

//

//

`define RESET_VECTOR    64'hFFFF_FFFF_FFFF_FFF0

`define RESET_VECTOR    64'hFFFF_FFFF_FFFF_FFF0

`define NMI_VECTOR              64'hFFFF_FFFF_FFFF_FFE0

`define NMI_VECTOR              64'hFFFF_FFFF_FFFF_FFE0

`define IRQ_VECTOR              64'hFFFF_FFFF_FFFF_FFD0

`define IRQ_VECTOR              64'hFFFF_FFFF_FFFF_FFD0

`define TRAP_VECTOR             64'h0000_0000_0000_0000

`define TRAP_VECTOR             64'h0000_0000_0000_0000

`define MISC    7'd0

`define MISC    7'd0

`define         BRK             7'd0

`define         BRK             7'd0

`define         IRQ             7'd1

`define         IRQ             7'd1

`define     FIP         7'd20

`define     FIP         7'd20

`define         IRET    7'd32

`define         IRET    7'd32

`define         ERET    7'd33

`define         ERET    7'd33

`define         WAIT    7'd40

`define         WAIT    7'd40

`define         TLBP    7'd49

`define         TLBP    7'd49

`define         AXC             6'd21

`define         AXC             6'd21

`define                 Tick                    6'd22

`define                 Tick                    6'd22

`define                 EPC                             6'd23

`define                 EPC                             6'd23

`define                 CauseCode               6'd24

`define                 CauseCode               6'd24

`define                 TBA                             6'd25

`define                 TBA                             6'd25

`define         OMG             7'd50

`define         OMG             7'd50

`define         CMG             7'd51

`define         CMG             7'd51

`define         OMGI    7'd52

`define         OMGI    7'd52

`define         CMGI    7'd53

`define         CMGI    7'd53

`define RR      7'd2

`define RR      7'd2

`define         ADD             7'd2

`define         ADD             7'd2

`define         ADDU    7'd3

`define         ADDU    7'd3

`define         SUB             7'd4

`define         SUB             7'd4

`define         SUBU    7'd5

`define         SUBU    7'd5

reg [1:0] rm;            // fp rounding mode

reg [1:0] rm;            // fp rounding mode

reg [41:0] dIR;

reg [41:0] dIR;

reg [41:0] xIR;

reg [41:0] xIR;

reg [63:0] pc;

reg [63:0] pc;

reg [63:0] ErrorEPC,EPC,IPC;

reg [63:0] ErrorEPC,EPC,IPC;

reg [63:0] xpc;

reg [63:0] xpc;

reg [63:0] tlbra;                // return address for a TLB exception

reg [63:0] tlbra;                // return address for a TLB exception

reg [8:0] dRa,dRb,dRc;

reg [8:0] dRa,dRb,dRc;

reg [8:0] xRt;

reg [8:0] xRt;

reg [63:0] dImm;

reg [63:0] dImm;

reg [63:0] ea;

reg [63:0] ea;

reg [63:0] iadr_o;

reg [63:0] iadr_o;

reg [31:0] idat;

reg [31:0] idat;

reg [4:0] cstate;

reg [4:0] cstate;

reg dbranch_taken,xbranch_taken;

reg dbranch_taken,xbranch_taken;

reg [63:0] mutex_gate;

reg [63:0] mutex_gate;

reg [63:0] TBA;

reg [63:0] TBA;

reg [3:0] AXC,dAXC,xAXC;

reg [3:0] AXC,dAXC,xAXC;

reg dtinit;

reg dtinit;

//reg wr_icache;

//reg wr_icache;

reg dccyc;

reg dccyc;

wire [63:0] cdat;

wire [63:0] cdat;

reg [63:0] wr_addr;

reg [63:0] wr_addr;

wire KernelMode = StatusEXL;

wire KernelMode = StatusEXL;

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

// TLB

// TLB

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

reg [24:13] TLBPageMask;

reg [24:13] TLBPageMask;

reg [63:13] TLBVirtPage;

reg [63:13] TLBVirtPage;

reg [63:13] TLBPhysPage0;

reg [63:13] TLBPhysPage0;

reg [63:13] TLBPhysPage1;

reg [63:13] TLBPhysPage1;

reg [7:0] TLBASID;

reg [7:0] TLBASID;

reg TLBG;

reg TLBG;

reg TLBD;

reg TLBD;

reg TLBValid;

reg TLBValid;

reg [63:0] Index;

reg [63:0] Index;

reg [15:0] IMatch,DMatch;

reg [15:0] IMatch,DMatch;

reg [15:0] ITLBValid;

reg [15:0] ITLBValid;

initial begin

initial begin

        begin

        begin

                ITLBPageMask[n] = 0;

                ITLBPageMask[n] = 0;

                ITLBVirtPage[n] = 0;

                ITLBVirtPage[n] = 0;

                ITLBPhysPage0[n] = 0;

                ITLBPhysPage0[n] = 0;

                ITLBPhysPage1[n] = 0;

                ITLBPhysPage1[n] = 0;

                ITLBASID[n] = 0;

                ITLBASID[n] = 0;

                ITLBValid[n] = 0;

                ITLBValid[n] = 0;

        end

        end

end

end

always @*

always @*

always @(IMatch)

always @(IMatch)

assign ppc[12:0] = pc[12:0];

assign ppc[12:0] = pc[12:0];

always @(ea)

always @(ea)

always @(DMatch)

always @(DMatch)

assign pea[12:0] = ea[12:0];

assign pea[12:0] = ea[12:0];

wire dram_bus = !pea[63];

wire dram_bus = !pea[63];

wire m2_dram_bus = !m2Addr[63];

wire m2_dram_bus = !m2Addr[63];

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

// Clock control

// Clock control

// - reset or NMI reenables the clock

// - reset or NMI reenables the clock

// - this circuit must be under the clk_i domain

// - this circuit must be under the clk_i domain

// Instruction Cache

// Instruction Cache

// 8kB

// 8kB

// 

// 

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

reg icaccess;

reg icaccess;

//Raptor64_icache_ram_x32 u1

//Raptor64_icache_ram_x32 u1

//(

//(

//      .clk(clk),

//      .clk(clk),

//      .wr(icaccess & ack_i),

//      .wr(icaccess & ack_i),

//      .adr_i(adr_o[12:0]),

//      .adr_i(adr_o[12:0]),

//      .dat_i(dat_i),

//      .dat_i(dat_i),

//      .pc(pc),

//      .pc(pc),

//      .insn(insn)

//      .insn(insn)

//);

//);

wire [127:0] insnbundle;

wire [127:0] insnbundle;

Raptor64_icache_ram u1

Raptor64_icache_ram u1

(

(

        .clka(clk), // input clka

        .clka(clk), // input clka

        .wea(icaccess & ack_i), // input [0 : 0] wea

        .wea(icaccess & ack_i), // input [0 : 0] wea

        .clkb(~clk), // input clkb

        .clkb(~clk), // input clkb

        .addrb(pc[12:4]), // input [9 : 0] addrb

        .addrb(pc[12:4]), // input [9 : 0] addrb

        .doutb(insnbundle) // output [63 : 0] doutb

        .doutb(insnbundle) // output [63 : 0] doutb

);

);

begin

begin

        endcase

        endcase

end

end

reg [63:13] tmem [127:0];

reg [63:13] tmem [127:0];

end

end

wire [64:13] tgout;

wire [64:13] tgout;

assign tgout = {tvalid[pc[12:6]],tmem[pc[12:6]]};

assign tgout = {tvalid[pc[12:6]],tmem[pc[12:6]]};

assign ihit = (tgout=={1'b1,ppc[63:13]});

assign ihit = (tgout=={1'b1,ppc[63:13]});

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

// Data Cache

// Data Cache

// No-allocate on write

// No-allocate on write

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

reg [64:0] xData;

reg [64:0] xData;

reg m1IsCacheElement;

reg m1IsCacheElement;

reg nopI;

reg nopI;

wire [6:0] iFunc = insn[6:0];

wire [6:0] iFunc = insn[6:0];

wire [6:0] dFunc = dIR[6:0];

wire [6:0] dFunc = dIR[6:0];

wire [6:0] xFunc = xIR[6:0];

wire [6:0] xFunc = xIR[6:0];

wire [6:0] iOpcode = insn[41:35];

wire [6:0] iOpcode = insn[41:35];

wire [6:0] xOpcode = xIR[41:35];

wire [6:0] xOpcode = xIR[41:35];

wire [6:0] dOpcode = dIR[41:35];

wire [6:0] dOpcode = dIR[41:35];

reg [63:0] tick;

reg [63:0] tick;

reg [63:0] tba;

reg [63:0] tba;

reg [63:0] exception_address,ipc;

reg [63:0] exception_address,ipc;

reg [63:0] a,b,c,imm,m1b;

reg [63:0] a,b,c,imm,m1b;

reg prev_ihit;

reg prev_ihit;

reg rsf;

reg rsf;

reg [63:5] resv_address;

reg [63:5] resv_address;

reg xirqf;

reg xirqf;

reg [7:0] xextype;

reg [7:0] xextype;

wire advanceX_edge;

wire advanceX_edge;

reg takb;

reg takb;

wire [127:0] mult_out;

wire [127:0] mult_out;

endfunction

endfunction

wire [63:0] jmp_tgt = dOpcode[6:4]==`IMM ? {dIR[26:0],insn[34:0],2'b00} : {pc[63:37],insn[34:0],2'b00};

wire [63:0] jmp_tgt = dOpcode[6:4]==`IMM ? {dIR[26:0],insn[34:0],2'b00} : {pc[63:37],insn[34:0],2'b00};

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

// Branch history table.

// Branch history table.

// The history table is updated by the EX stage and read in

// The history table is updated by the EX stage and read in

// both the EX and IF stages.

// both the EX and IF stages.

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

reg [2:0] gbl_branch_hist;

reg [2:0] gbl_branch_hist;

// In the real world we don't care.

// In the real world we don't care.

initial begin

initial begin

        for (n = 0; n < 256; n = n + 1)

        for (n = 0; n < 256; n = n + 1)

                branch_history_table[n] = 0;

                branch_history_table[n] = 0;

end

end

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

// Evaluate branch conditions.

// Evaluate branch conditions.

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

wire signed [63:0] as = a;

wire signed [63:0] as = a;

wire aeqz = a==64'd0;

wire aeqz = a==64'd0;

wire beqz = b==64'd0;

wire beqz = b==64'd0;

wire immeqz = imm==64'd0;

wire immeqz = imm==64'd0;

wire eq = a==b;

wire eq = a==b;

wire eqi = a==imm;

wire eqi = a==imm;

wire lti = as < imms;

wire lti = as < imms;

wire ltu = a < b;

wire ltu = a < b;

wire ltui = a < imm;

wire ltui = a < imm;

always @(xOpcode or xFunc or a or eq or eqi or lt or lti or ltu or ltui or aeqz or beqz or rsf or xIR)

always @(xOpcode or xFunc or a or eq or eqi or lt or lti or ltu or ltui or aeqz or beqz or rsf or xIR)

);

);

always @(xOpcode or xFunc or a or b or imm or as or bs or imms or xpc or

always @(xOpcode or xFunc or a or b or imm or as or bs or imms or xpc or

        sqrt_out or cntlzo or cntloo or tick or ipc or tba or AXC or

        sqrt_out or cntlzo or cntloo or tick or ipc or tba or AXC or

        lt or eq or ltu or mult_out or lti or eqi or ltui or xIR or div_q or div_r or

        lt or eq or ltu or mult_out or lti or eqi or ltui or xIR or div_q or div_r or

        PageTableAddr or BadVAddr or ASID or TLBPageMask

        PageTableAddr or BadVAddr or ASID or TLBPageMask

)

)

casex(xOpcode)

casex(xOpcode)

`R:

`R:

        casex(xFunc)

        casex(xFunc)