| Line 19... |
Line 19... |
// You should have received a copy of the GNU General Public License
|
// You should have received a copy of the GNU General Public License
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
//
|
//
|
// ============================================================================
|
// ============================================================================
|
//
|
//
|
//`define RAS_PREDICTION 1
|
`define ADDRESS_RESERVATION 1
|
|
`define RAS_PREDICTION 1
|
//`define BTB 1
|
//`define BTB 1
|
//`define TLB 1
|
//`define TLB 1
|
//`define BRANCH_PREDICTION_SIMPLE 1
|
//`define BRANCH_PREDICTION_SIMPLE 1
|
|
|
`define RESET_VECTOR 64'hFFFF_FFFF_FFFF_FFF0
|
`define RESET_VECTOR 64'hFFFF_FFFF_FFFF_FFF0
|
| Line 74... |
Line 75... |
`define MISC 7'd0
|
`define MISC 7'd0
|
`define BRK 7'd0
|
`define BRK 7'd0
|
`define IRQ 7'd1
|
`define IRQ 7'd1
|
`define ICACHE_ON 7'd10
|
`define ICACHE_ON 7'd10
|
`define ICACHE_OFF 7'd11
|
`define ICACHE_OFF 7'd11
|
|
`define DCACHE_ON 7'd12
|
|
`define DCACHE_OFF 7'd13
|
`define FIP 7'd20
|
`define FIP 7'd20
|
`define IRET 7'd32
|
`define IRET 7'd32
|
`define ERET 7'd33
|
`define ERET 7'd33
|
`define WAIT 7'd40
|
`define WAIT 7'd40
|
`define TLBP 7'd49
|
`define TLBP 7'd49
|
| Line 89... |
Line 92... |
`define R 7'd1
|
`define R 7'd1
|
`define COM 7'd4
|
`define COM 7'd4
|
`define NOT 7'd5
|
`define NOT 7'd5
|
`define NEG 7'd6
|
`define NEG 7'd6
|
`define ABS 7'd7
|
`define ABS 7'd7
|
|
`define MOV 7'd9
|
`define SWAP 7'd13
|
`define SWAP 7'd13
|
`define CTLZ 7'd16
|
`define CTLZ 7'd16
|
`define CTLO 7'd17
|
`define CTLO 7'd17
|
`define CTPOP 7'd18
|
`define CTPOP 7'd18
|
`define SEXT8 7'd19
|
`define SEXT8 7'd19
|
| Line 122... |
Line 126... |
`define Tick 6'd22
|
`define Tick 6'd22
|
`define EPC 6'd23
|
`define EPC 6'd23
|
`define CauseCode 6'd24
|
`define CauseCode 6'd24
|
`define TBA 6'd25
|
`define TBA 6'd25
|
`define NON_ICACHE_SEG 6'd26
|
`define NON_ICACHE_SEG 6'd26
|
|
`define FPCR 6'd32
|
|
`define IPC 6'd33
|
`define OMG 7'd50
|
`define OMG 7'd50
|
`define CMG 7'd51
|
`define CMG 7'd51
|
`define OMGI 7'd52
|
`define OMGI 7'd52
|
`define CMGI 7'd53
|
`define CMGI 7'd53
|
`define EXEC 7'd58
|
`define EXEC 7'd58
|
|
`define MYST 7'd59
|
`define RR 7'd2
|
`define RR 7'd2
|
`define ADD 7'd2
|
`define ADD 7'd2
|
`define ADDU 7'd3
|
`define ADDU 7'd3
|
`define SUB 7'd4
|
`define SUB 7'd4
|
`define SUBU 7'd5
|
`define SUBU 7'd5
|
| Line 186... |
Line 193... |
`define ROLAMI 7'd5
|
`define ROLAMI 7'd5
|
`define BFINS 7'd8
|
`define BFINS 7'd8
|
`define BFSET 7'd9
|
`define BFSET 7'd9
|
`define BFCLR 7'd10
|
`define BFCLR 7'd10
|
`define BFCHG 7'd11
|
`define BFCHG 7'd11
|
|
|
`define ADDI 7'd4
|
`define ADDI 7'd4
|
`define ADDUI 7'd5
|
`define ADDUI 7'd5
|
`define SUBI 7'd6
|
`define SUBI 7'd6
|
`define SUBUI 7'd7
|
`define SUBUI 7'd7
|
`define CMPI 7'd8
|
`define CMPI 7'd8
|
| Line 279... |
Line 285... |
`define OUTB 7'd72
|
`define OUTB 7'd72
|
`define OUTC 7'd73
|
`define OUTC 7'd73
|
`define OUTH 7'd74
|
`define OUTH 7'd74
|
`define OUTW 7'd75
|
`define OUTW 7'd75
|
|
|
|
`define LM 7'd78
|
|
`define SM 7'd79
|
|
|
`define BLTI 7'd80
|
`define BLTI 7'd80
|
`define BGEI 7'd81
|
`define BGEI 7'd81
|
`define BLEI 7'd82
|
`define BLEI 7'd82
|
`define BGTI 7'd83
|
`define BGTI 7'd83
|
`define BLTUI 7'd84
|
`define BLTUI 7'd84
|
`define BGEUI 7'd85
|
`define BGEUI 7'd85
|
`define BLEUI 7'd86
|
`define BLEUI 7'd86
|
`define BGTUI 7'd87
|
`define BGTUI 7'd87
|
`define BEQI 7'd88
|
`define BEQI 7'd88
|
`define BNEI 7'd89
|
`define BNEI 7'd89
|
`define BRAI 7'd90
|
|
`define BRNI 7'd91
|
|
|
|
`define BTRI 7'd94
|
`define BTRI 7'd94
|
`define BLTRI 5'd0
|
`define BLTRI 5'd0
|
`define BGERI 5'd1
|
`define BGERI 5'd1
|
`define BLERI 5'd2
|
`define BLERI 5'd2
|
| Line 323... |
Line 330... |
`define BRA 5'd10
|
`define BRA 5'd10
|
`define BRN 5'd11
|
`define BRN 5'd11
|
`define BAND 5'd12
|
`define BAND 5'd12
|
`define BOR 5'd13
|
`define BOR 5'd13
|
`define BNR 5'd14
|
`define BNR 5'd14
|
|
`define LOOP 5'd15
|
`define BLTR 5'd16
|
`define BLTR 5'd16
|
`define BGER 5'd17
|
`define BGER 5'd17
|
`define BLER 5'd18
|
`define BLER 5'd18
|
`define BGTR 5'd19
|
`define BGTR 5'd19
|
`define BLTUR 5'd20
|
`define BLTUR 5'd20
|
| Line 415... |
Line 423... |
input sys_adv;
|
input sys_adv;
|
input [63:5] sys_adr;
|
input [63:5] sys_adr;
|
|
|
reg resetA;
|
reg resetA;
|
reg im,bu_im; // interrupt mask
|
reg im,bu_im; // interrupt mask
|
|
reg im1; // temporary interrupt mask for LM/SM
|
reg [1:0] rm; // fp rounding mode
|
reg [1:0] rm; // fp rounding mode
|
reg [41:0] dIR;
|
reg [41:0] dIR;
|
|
reg [41:0] ndIR;
|
|
wire [6:0] dOpcode = dIR[41:35];
|
reg [41:0] xIR;
|
reg [41:0] xIR;
|
reg [63:0] pc;
|
reg [63:0] pc;
|
reg [63:0] ErrorEPC,EPC,IPC;
|
reg [63:0] ErrorEPC,EPC,IPC;
|
reg [63:0] dpc,m1pc,m2pc,wpc;
|
reg [63:0] dpc,m1pc,m2pc,wpc;
|
reg dpcv,xpcv,m1pcv,m2pcv,wpcv; // PC valid indicators
|
reg dpcv,xpcv,m1pcv,m2pcv,wpcv; // PC valid indicators
|
| Line 438... |
Line 449... |
reg [63:0] mutex_gate;
|
reg [63:0] mutex_gate;
|
reg [63:0] TBA;
|
reg [63:0] TBA;
|
reg [1:0] dhwxtype,xhwxtype,m1hwxtype,m2hwxtype,whwxtype;
|
reg [1:0] dhwxtype,xhwxtype,m1hwxtype,m2hwxtype,whwxtype;
|
reg [3:0] AXC,dAXC,xAXC;
|
reg [3:0] AXC,dAXC,xAXC;
|
reg dtinit;
|
reg dtinit;
|
|
reg dcache_on;
|
reg [63:32] nonICacheSeg;
|
reg [63:32] nonICacheSeg;
|
|
|
//reg wr_icache;
|
|
reg dccyc;
|
reg dccyc;
|
wire [63:0] cdat;
|
wire [63:0] cdat;
|
reg [63:0] wr_addr;
|
reg [63:0] wr_addr;
|
reg [41:0] insn;
|
reg [41:0] insn;
|
wire [63:0] rfoa,rfob;
|
wire [63:0] rfoa,rfob;
|
| Line 600... |
Line 611... |
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Instruction Cache
|
// Instruction Cache
|
// 8kB
|
// 8kB
|
//
|
//
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
|
//reg lfdir;
|
|
wire lfdir = ((dOpcode==`LM || dOpcode==`SM) && dIR[31:0]!=32'd0) && ndIR[31:0]!=32'd0;
|
|
wire ldnop = ((dOpcode==`LM || dOpcode==`SM) && (dIR[31:0]==32'd0 || ndIR[31:0]==32'd0));
|
reg icaccess;
|
reg icaccess;
|
//wire nonICachedArea;
|
|
|
|
//Raptor64_icache_ram_x32 u1
|
|
//(
|
|
// .clk(clk),
|
|
// .wr(icaccess & ack_i),
|
|
// .adr_i(adr_o[12:0]),
|
|
// .dat_i(dat_i),
|
|
// .pc(pc),
|
|
// .insn(insn)
|
|
//);
|
|
reg ICacheOn;
|
reg ICacheOn;
|
wire ibufrdy;
|
wire ibufrdy;
|
reg [63:0] tmpbuf;
|
reg [63:0] tmpbuf;
|
wire [127:0] insnbundle;
|
wire [127:0] insnbundle;
|
reg [127:0] insnbuf;
|
reg [127:0] insnbuf0,insnbuf1;
|
reg [63:4] ibuftag;
|
reg [63:4] ibuftag0,ibuftag1;
|
wire isICached = ppc[63:32]!=nonICacheSeg;
|
wire isICached = ppc[63:32]!=nonICacheSeg;
|
wire ICacheAct = ICacheOn & isICached;
|
wire ICacheAct = ICacheOn & isICached;
|
|
|
Raptor64_icache_ram u1
|
Raptor64_icache_ram u1
|
(
|
(
|
.clka(clk), // input clka
|
.clka(clk), // input clka
|
.wea(icaccess & ack_i), // input [0 : 0] wea
|
.wea(icaccess & ack_i), // input [0 : 0] wea
|
.addra(adr_o[12:3]), // input [9 : 0] addra
|
.addra(adr_o[12:3]), // input [9 : 0] addra
|
.dina(dat_i), // input [63 : 0] dina
|
.dina(dat_i), // input [63 : 0] dina
|
.clkb(~clk), // input clkb
|
.clkb(~clk), // input clkb
|
.addrb(pc[12:4]), // input [9 : 0] addrb
|
.addrb(pc[12:4]), // input [8 : 0] addrb
|
.doutb(insnbundle) // output [63 : 0] doutb
|
.doutb(insnbundle) // output [127 : 0] doutb
|
);
|
);
|
|
|
always @(pc or insnbundle or ICacheAct or insnbuf)
|
always @(ppc or insnbundle or ICacheAct or insnbuf0 or insnbuf1 or ndIR or lfdir or ldnop)
|
begin
|
begin
|
case({ICacheAct,pc[3:2]})
|
casex({ldnop,lfdir,ICacheAct,ibuftag1==ppc[63:4],pc[3:2]})
|
3'd0: insn <= insnbuf[ 41: 0];
|
6'b1xxxxx: insn <= 42'h37800000000;
|
3'd1: insn <= insnbuf[ 83:42];
|
6'b01xxxx: insn <= ndIR;
|
3'd2: insn <= insnbuf[125:84];
|
6'b001x00: insn <= insnbundle[ 41: 0];
|
3'd3: insn <= 42'h37800000000;
|
6'b001x01: insn <= insnbundle[ 83:42];
|
3'd4: insn <= insnbundle[ 41: 0];
|
6'b001x10: insn <= insnbundle[125:84];
|
3'd5: insn <= insnbundle[ 83:42];
|
6'b001x11: insn <= 42'h37800000000; // NOP instruction
|
3'd6: insn <= insnbundle[125:84];
|
6'b000000: insn <= insnbuf0[ 41: 0];
|
3'd7: insn <= 42'h37800000000; // NOP instruction
|
6'b000001: insn <= insnbuf0[ 83:42];
|
|
6'b000010: insn <= insnbuf0[125:84];
|
|
6'b000011: insn <= 42'h37800000000;
|
|
6'b000100: insn <= insnbuf1[ 41: 0];
|
|
6'b000101: insn <= insnbuf1[ 83:42];
|
|
6'b000110: insn <= insnbuf1[125:84];
|
|
6'b000111: insn <= 42'h37800000000;
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
reg [63:13] tmem [127:0];
|
reg [63:13] tmem [127:0];
|
| Line 660... |
Line 669... |
end
|
end
|
|
|
wire [64:13] tgout;
|
wire [64:13] tgout;
|
assign tgout = {tvalid[pc[12:6]],tmem[pc[12:6]]};
|
assign tgout = {tvalid[pc[12:6]],tmem[pc[12:6]]};
|
assign ihit = (tgout=={1'b1,ppc[63:13]});
|
assign ihit = (tgout=={1'b1,ppc[63:13]});
|
assign ibufrdy = ibuftag==ppc[63:4];
|
assign ibufrdy = ibuftag0==ppc[63:4] || ibuftag1==ppc[63:4];
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Data Cache
|
// Data Cache
|
// No-allocate on write
|
// No-allocate on write
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
| Line 675... |
Line 684... |
reg [7:0] dsel_o;
|
reg [7:0] dsel_o;
|
reg [63:0] dadr_o;
|
reg [63:0] dadr_o;
|
reg [31:0] ddat;
|
reg [31:0] ddat;
|
reg wr_dcache;
|
reg wr_dcache;
|
|
|
// cache RAM 16Kb
|
// cache RAM 32Kb
|
/*Raptor64_dcache_ram u10
|
|
(
|
|
.clk(clk),
|
|
.wr(dcaccess ? wr_dcache : wrhit ? (dram_bus ? wr_en: we_o): 1'b0),
|
|
.sel(dcaccess ? 4'b1111 : wrhit ? ~wr_mask : 4'b0000),
|
|
.wadr(dcaccess ? dadr_o[13:2] : wr_addr[13:2]),
|
|
.i(dcaccess ? ddat : wr_data),
|
|
.radr(pea[13:3]),
|
|
.o(cdat)
|
|
);
|
|
*/
|
|
Raptor64_dcache_ram u10
|
Raptor64_dcache_ram u10
|
(
|
(
|
.clka(clk), // input clka
|
.clka(clk), // input clka
|
.ena(1'b1),
|
.ena(1'b1),
|
.wea(dcaccess ? {8{ack_i}} : wrhit ? sel_o : 8'h00), // input [7 : 0] wea
|
.wea(dcaccess ? {8{ack_i}} : wrhit ? sel_o : 8'h00), // input [7 : 0] wea
|
.addra(adr_o[14:3]), // input [11 : 0] addra
|
.addra(adr_o[14:3]), // input [11 : 0] addra
|
.dina(dcaccess ? dat_i : dat_o), // input [63 : 0] dina
|
.dina(dcaccess ? dat_i : dat_o), // input [63 : 0] dina
|
|
|
.clkb(~clk), // input clkb
|
.clkb(~clk), // input clkb
|
.addrb(adr_o[14:3]), // input [11 : 0] addrb
|
.addrb(pea[14:3]), // input [11 : 0] addrb
|
.doutb(cdat) // output [63 : 0] doutb
|
.doutb(cdat) // output [63 : 0] doutb
|
);
|
);
|
|
|
|
|
Raptor64_dcache_tagram u11
|
Raptor64_dcache_tagram u11
|
| Line 713... |
Line 711... |
|
|
.clkb(~clk), // input clkb
|
.clkb(~clk), // input clkb
|
.addrb({1'b0,pea[14:6]}), // input [9 : 0] addrb
|
.addrb({1'b0,pea[14:6]}), // input [9 : 0] addrb
|
.doutb(dtgout) // output [48 : 0] doutb
|
.doutb(dtgout) // output [48 : 0] doutb
|
);
|
);
|
// tag ram
|
|
//syncRam512x64_1rw1r u11
|
|
//(
|
|
// .wrst(1'b0),
|
|
// .wclk(clk),
|
|
// .wce(adr_o[4:2]==3'b111),
|
|
// .we(ack_i),
|
|
// .wadr(adr_o[14:5]),
|
|
// .i({14'h3FFF,dadr_o[63:14]}),
|
|
// .wo(),
|
|
//
|
|
// .rrst(1'b0),
|
|
// .rclk(~clk),
|
|
// .rce(1'b1),
|
|
// .radr(pea[13:5]),
|
|
// .ro({dtign,dtgout})
|
|
//);
|
|
|
|
assign dhit = (dtgout=={1'b1,pea[63:15]});
|
assign dhit = (dtgout=={1'b1,pea[63:15]});
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
|
|
reg [64:0] xData;
|
reg [64:0] xData;
|
wire xisCacheElement = xData[63:52] != 12'hFFD && xData[63:52]!=12'hFFF;
|
wire xisCacheElement = (xData[63:52] != 12'hFFD && xData[63:52]!=12'hFFF) && dcache_on;
|
reg m1IsCacheElement;
|
reg m1IsCacheElement;
|
|
|
reg nopI;
|
reg nopI;
|
wire [6:0] iFunc = insn[6:0];
|
wire [6:0] iFunc = insn[6:0];
|
wire [6:0] dFunc = dIR[6:0];
|
wire [6:0] dFunc = dIR[6:0];
|
wire [6:0] xFunc = xIR[6:0];
|
wire [6:0] xFunc = xIR[6:0];
|
wire [6:0] iOpcode = insn[41:35];
|
wire [6:0] iOpcode = insn[41:35];
|
wire [6:0] xOpcode = xIR[41:35];
|
wire [6:0] xOpcode = xIR[41:35];
|
wire [6:0] dOpcode = dIR[41:35];
|
|
reg [6:0] m1Opcode,m2Opcode;
|
reg [6:0] m1Opcode,m2Opcode;
|
reg [6:0] m1Func,m2Func;
|
reg [6:0] m1Func,m2Func;
|
reg [63:0] m1Data,m2Data,wData,tData;
|
reg [63:0] m1Data,m2Data,wData,tData;
|
reg [63:0] m2Addr;
|
reg [63:0] m2Addr;
|
reg [63:0] tick;
|
reg [63:0] tick;
|
| Line 930... |
Line 910... |
6'b111111: popcnt6 = 3'd6;
|
6'b111111: popcnt6 = 3'd6;
|
endcase
|
endcase
|
end
|
end
|
endfunction
|
endfunction
|
|
|
|
function [5:0] popcnt36;
|
|
input [35:0] a;
|
|
begin
|
|
popcnt36 = popcnt6(a[5:0]) +
|
|
popcnt6(a[11:6]) +
|
|
popcnt6(a[17:12]) +
|
|
popcnt6(a[23:18]) +
|
|
popcnt6(a[29:24]) +
|
|
popcnt6(a[35:30]);
|
|
end
|
|
endfunction
|
|
|
wire [63:0] jmp_tgt = dOpcode[6:4]==`IMM ? {dIR[26:0],insn[34:0],2'b00} : {pc[63:37],insn[34:0],2'b00};
|
wire [63:0] jmp_tgt = dOpcode[6:4]==`IMM ? {dIR[26:0],insn[34:0],2'b00} : {pc[63:37],insn[34:0],2'b00};
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
|
// Stack for return address predictor
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
`ifdef RAS_PREDICTION
|
`ifdef RAS_PREDICTION
|
reg [63:0] ras [63:0]; // return address stack, return predictions
|
reg [63:0] ras [63:0]; // return address stack, return predictions
|
reg [5:0] ras_sp;
|
reg [5:0] ras_sp; // stack pointer
|
`endif
|
`endif
|
`ifdef BTB
|
`ifdef BTB
|
reg [63:0] btb [63:0]; // branch target buffer
|
reg [63:0] btb [63:0]; // branch target buffer
|
`endif
|
`endif
|
|
|
| Line 977... |
Line 970... |
wire [7:0] bht_ra2 = {pc[5:0],gbl_branch_hist[2:1]}; // read address (IF stage)
|
wire [7:0] bht_ra2 = {pc[5:0],gbl_branch_hist[2:1]}; // read address (IF stage)
|
wire [1:0] bht_xbits = branch_history_table[bht_ra1];
|
wire [1:0] bht_xbits = branch_history_table[bht_ra1];
|
wire [1:0] bht_ibits = branch_history_table[bht_ra2];
|
wire [1:0] bht_ibits = branch_history_table[bht_ra2];
|
wire predict_taken = bht_ibits==2'd0 || bht_ibits==2'd1;
|
wire predict_taken = bht_ibits==2'd0 || bht_ibits==2'd1;
|
|
|
wire isxBranchI = (xOpcode==`BRAI || xOpcode==`BRNI || xOpcode==`BEQI || xOpcode==`BNEI ||
|
wire isxBranchI = (xOpcode==`BEQI || xOpcode==`BNEI ||
|
xOpcode==`BLTI || xOpcode==`BLEI || xOpcode==`BGTI || xOpcode==`BGEI ||
|
xOpcode==`BLTI || xOpcode==`BLEI || xOpcode==`BGTI || xOpcode==`BGEI ||
|
xOpcode==`BLTUI || xOpcode==`BLEUI || xOpcode==`BGTUI || xOpcode==`BGEUI)
|
xOpcode==`BLTUI || xOpcode==`BLEUI || xOpcode==`BGTUI || xOpcode==`BGEUI)
|
;
|
;
|
wire isxBranch = isxBranchI || xOpcode==`TRAPcc || xOpcode==`TRAPcci || xOpcode==`BTRI || xOpcode==`BTRR;
|
wire isxBranch = isxBranchI || xOpcode==`TRAPcc || xOpcode==`TRAPcci || xOpcode==`BTRI || xOpcode==`BTRR;
|
|
|
| Line 1042... |
Line 1035... |
`BGTU: takb = !(ltu|eq);
|
`BGTU: takb = !(ltu|eq);
|
`BGEU: takb = !ltu;
|
`BGEU: takb = !ltu;
|
`BOR: takb = !aeqz || !beqz;
|
`BOR: takb = !aeqz || !beqz;
|
`BAND: takb = !aeqz && !beqz;
|
`BAND: takb = !aeqz && !beqz;
|
`BNR: takb = !rsf;
|
`BNR: takb = !rsf;
|
|
`LOOP: takb = !beqz;
|
`BEQR: takb = eq;
|
`BEQR: takb = eq;
|
`BNER: takb = !eq;
|
`BNER: takb = !eq;
|
`BLTR: takb = lt;
|
`BLTR: takb = lt;
|
`BLER: takb = lt|eq;
|
`BLER: takb = lt|eq;
|
`BGTR: takb = !(lt|eq);
|
`BGTR: takb = !(lt|eq);
|
| Line 1054... |
Line 1048... |
`BLEUR: takb = ltu|eq;
|
`BLEUR: takb = ltu|eq;
|
`BGTUR: takb = !(ltu|eq);
|
`BGTUR: takb = !(ltu|eq);
|
`BGEUR: takb = !ltu;
|
`BGEUR: takb = !ltu;
|
default: takb = 1'b0;
|
default: takb = 1'b0;
|
endcase
|
endcase
|
`BRAI: takb = 1'b1;
|
|
`BRNI: takb = 1'b0;
|
|
`BEQI: takb = eqi;
|
`BEQI: takb = eqi;
|
`BNEI: takb = !eqi;
|
`BNEI: takb = !eqi;
|
`BLTI: takb = lti;
|
`BLTI: takb = lti;
|
`BLEI: takb = lti|eqi;
|
`BLEI: takb = lti|eqi;
|
`BGTI: takb = !(lti|eqi);
|
`BGTI: takb = !(lti|eqi);
|
| Line 1157... |
Line 1149... |
shfto or masko or bcdaddo or bcdsubo or fpLooOut or fpZLOut
|
shfto or masko or bcdaddo or bcdsubo or fpLooOut or fpZLOut
|
`ifdef TLB
|
`ifdef TLB
|
or Wired or Index or Random or TLBPhysPage0 or TLBPhysPage1 or TLBVirtPage or TLBASID or
|
or Wired or Index or Random or TLBPhysPage0 or TLBPhysPage1 or TLBVirtPage or TLBASID or
|
PageTableAddr or BadVAddr or ASID or TLBPageMask
|
PageTableAddr or BadVAddr or ASID or TLBPageMask
|
`endif
|
`endif
|
|
or ASID or EPC or mutex_gate or IPC or CauseCode or TBA or xAXC or nonICacheSeg or rm
|
)
|
)
|
casex(xOpcode)
|
casex(xOpcode)
|
`R:
|
`R:
|
casex(xFunc)
|
casex(xFunc)
|
`COM: xData = ~a;
|
`COM: xData = ~a;
|
`NOT: xData = ~|a;
|
`NOT: xData = ~|a;
|
`NEG: xData = -a;
|
`NEG: xData = -a;
|
`ABS: xData = a[63] ? -a : a;
|
`ABS: xData = a[63] ? -a : a;
|
|
`MOV: xData = a;
|
`SQRT: xData = sqrt_out;
|
`SQRT: xData = sqrt_out;
|
`SWAP: xData = {a[31:0],a[63:32]};
|
`SWAP: xData = {a[31:0],a[63:32]};
|
|
|
`REDOR: xData = |a;
|
`REDOR: xData = |a;
|
`REDAND: xData = &a;
|
`REDAND: xData = &a;
|
| Line 1212... |
Line 1206... |
`BadVAddr: xData = {BadVAddr,13'd0};
|
`BadVAddr: xData = {BadVAddr,13'd0};
|
`endif
|
`endif
|
`ASID: xData = ASID;
|
`ASID: xData = ASID;
|
`Tick: xData = tick;
|
`Tick: xData = tick;
|
`EPC: xData = EPC;
|
`EPC: xData = EPC;
|
|
`IPC: xData = IPC;
|
`CauseCode: xData = CauseCode;
|
`CauseCode: xData = CauseCode;
|
`TBA: xData = TBA;
|
`TBA: xData = TBA;
|
`AXC: xData = xAXC;
|
`AXC: xData = xAXC;
|
`NON_ICACHE_SEG: xData = nonICacheSeg;
|
`NON_ICACHE_SEG: xData = nonICacheSeg;
|
|
`FPCR: xData = {rm,30'd0};
|
default: xData = 65'd0;
|
default: xData = 65'd0;
|
endcase
|
endcase
|
`OMG: xData = mutex_gate[a[5:0]];
|
`OMG: xData = mutex_gate[a[5:0]];
|
`CMG: xData = mutex_gate[a[5:0]];
|
`CMG: xData = mutex_gate[a[5:0]];
|
`OMGI: begin
|
`OMGI: begin
|
| Line 1289... |
Line 1285... |
`BFSET: begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? 1'b1 : b[n]; xData[64] = 1'b0; end
|
`BFSET: begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? 1'b1 : b[n]; xData[64] = 1'b0; end
|
`BFCLR: begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? 1'b0 : b[n]; xData[64] = 1'b0; end
|
`BFCLR: begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? 1'b0 : b[n]; xData[64] = 1'b0; end
|
`BFCHG: begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? ~b[n] : b[n]; xData[64] = 1'b0; end
|
`BFCHG: begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? ~b[n] : b[n]; xData[64] = 1'b0; end
|
default: xData = 65'd0;
|
default: xData = 65'd0;
|
endcase
|
endcase
|
|
`BTRR:
|
|
case(xIR[4:0])
|
|
`LOOP: xData = b - 64'd1;
|
|
default: xData = 64'd0;
|
|
endcase
|
`SETLO: xData = {{32{xIR[31]}},xIR[31:0]};
|
`SETLO: xData = {{32{xIR[31]}},xIR[31:0]};
|
`SETHI: xData = {xIR[31:0],a[31:0]};
|
`SETHI: xData = {xIR[31:0],a[31:0]};
|
`ADDI: xData = a + imm;
|
`ADDI: xData = a + imm;
|
`ADDUI: xData = a + imm;
|
`ADDUI: xData = a + imm;
|
`SUBI: xData = a - imm;
|
`SUBI: xData = a - imm;
|
| Line 1318... |
Line 1319... |
`SGEUI: xData = !ltui;
|
`SGEUI: xData = !ltui;
|
`INB,`INCH,`INH,`INW:
|
`INB,`INCH,`INH,`INW:
|
xData = a + imm;
|
xData = a + imm;
|
`OUTB,`OUTC,`OUTH,`OUTW:
|
`OUTB,`OUTC,`OUTH,`OUTW:
|
xData = a + imm;
|
xData = a + imm;
|
`LW,`LH,`LC,`LB,`LHU,`LCU,`LBU,`LWR:
|
`LW,`LH,`LC,`LB,`LHU,`LCU,`LBU,`LWR,`LF,`LFD:
|
xData = a + imm;
|
xData = a + imm;
|
`SW,`SH,`SC,`SB,`SWC:
|
`SW,`SH,`SC,`SB,`SWC,`SF,`SFD:
|
xData = a + imm;
|
xData = a + imm;
|
`MEMNDX:
|
`MEMNDX:
|
xData = a + b + imm;
|
xData = a + b + imm;
|
`BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BOR,`BAND:
|
`SM: xData = a + {popcnt36(xIR[31:0]),3'b000};
|
xData = 64'd0;
|
`LM: xData = a + {popcnt36(xIR[31:0]),3'b000};
|
`TRAPcc: xData = fnIncPC(xpc);
|
`TRAPcc: xData = fnIncPC(xpc);
|
`TRAPcci: xData = fnIncPC(xpc);
|
`TRAPcci: xData = fnIncPC(xpc);
|
`CALL: xData = fnIncPC(xpc);
|
`CALL: xData = fnIncPC(xpc);
|
`JAL: xData = xpc + {xIR[29:25],2'b00};
|
`JAL: xData = xpc + {xIR[29:25],2'b00};
|
`RET: xData = a + {imm,2'b00};
|
`RET: xData = a + imm;
|
`FPLOO: xData = fpLooOut;
|
`FPLOO: xData = fpLooOut;
|
`FPZL: xData = fpZLOut;
|
`FPZL: xData = fpZLOut;
|
default: xData = 65'd0;
|
default: xData = 65'd0;
|
endcase
|
endcase
|
|
|
| Line 1355... |
Line 1356... |
xOpcode==`DIVSI || xOpcode==`DIVUI;
|
xOpcode==`DIVSI || xOpcode==`DIVUI;
|
|
|
wire xIsLoad =
|
wire xIsLoad =
|
xOpcode==`LW || xOpcode==`LH || xOpcode==`LB || xOpcode==`LWR ||
|
xOpcode==`LW || xOpcode==`LH || xOpcode==`LB || xOpcode==`LWR ||
|
xOpcode==`LHU || xOpcode==`LBU ||
|
xOpcode==`LHU || xOpcode==`LBU ||
|
xOpcode==`LC || xOpcode==`LCU ||
|
xOpcode==`LC || xOpcode==`LCU || xOpcode==`LM ||
|
xOpcode==`INW || xOpcode==`INB || xOpcode==`INH || xOpcode==`INCH
|
xOpcode==`LF || xOpcode==`LFD
|
;
|
;
|
wire xIsStore =
|
wire xIsStore =
|
xOpcode==`SW || xOpcode==`SH || xOpcode==`SB || xOpcode==`SC || xOpcode==`SWC ||
|
xOpcode==`SW || xOpcode==`SH || xOpcode==`SB || xOpcode==`SC || xOpcode==`SWC || xOpcode==`SM ||
|
|
xOpcode==`SF || xOpcode==`SFD ||
|
xOpcode==`OUTW || xOpcode==`OUTH || xOpcode==`OUTB || xOpcode==`OUTC
|
xOpcode==`OUTW || xOpcode==`OUTH || xOpcode==`OUTB || xOpcode==`OUTC
|
;
|
;
|
wire xIsSWC = xOpcode==`SWC;
|
wire xIsSWC = xOpcode==`SWC;
|
wire xIsIn =
|
wire xIsIn =
|
xOpcode==`INW || xOpcode==`INH || xOpcode==`INCH || xOpcode==`INB
|
xOpcode==`INW || xOpcode==`INH || xOpcode==`INCH || xOpcode==`INB
|
| Line 1375... |
Line 1377... |
// mOpcode==`LHU || mOpcode==`LBU || mOpcode==`LCU ||
|
// mOpcode==`LHU || mOpcode==`LBU || mOpcode==`LCU ||
|
// mOpcode==`INW || mOpcode==`INB || mOpcode==`INH
|
// mOpcode==`INW || mOpcode==`INB || mOpcode==`INH
|
// ;
|
// ;
|
wire m1IsLoad =
|
wire m1IsLoad =
|
m1Opcode==`LW || m1Opcode==`LH || m1Opcode==`LB || m1Opcode==`LC || m1Opcode==`LWR ||
|
m1Opcode==`LW || m1Opcode==`LH || m1Opcode==`LB || m1Opcode==`LC || m1Opcode==`LWR ||
|
m1Opcode==`LHU || m1Opcode==`LBU || m1Opcode==`LCU
|
m1Opcode==`LHU || m1Opcode==`LBU || m1Opcode==`LCU || m1Opcode==`LM ||
|
|
m1Opcode==`LF || m1Opcode==`LFD
|
;
|
;
|
wire m1IsIn =
|
wire m1IsIn =
|
m1Opcode==`INW || m1Opcode==`INH || m1Opcode==`INCH || m1Opcode==`INB
|
m1Opcode==`INW || m1Opcode==`INH || m1Opcode==`INCH || m1Opcode==`INB
|
;
|
;
|
wire m2IsInW = m2Opcode==`INW;
|
wire m2IsInW = m2Opcode==`INW;
|
wire m1IsStore =
|
wire m1IsStore = m1Opcode==`SW || m1Opcode==`SH || m1Opcode==`SB || m1Opcode==`SC || m1Opcode==`SWC || m1Opcode==`SM ||
|
m1Opcode==`SW || m1Opcode==`SH || m1Opcode==`SB || m1Opcode==`SC || m1Opcode==`SWC
|
m1Opcode==`SF || m1Opcode==`SFD;
|
;
|
wire m2IsStore = m2Opcode==`SW || m2Opcode==`SWC || m2Opcode==`SH || m2Opcode==`SC || m2Opcode==`SB || m2Opcode==`SM ||
|
|
m2Opcode==`SF || m2Opcode==`SFD;
|
wire xIsIO =
|
wire xIsIO =
|
xIsIn ||
|
xIsIn ||
|
xOpcode==`OUTW || xOpcode==`OUTH || xOpcode==`OUTC || xOpcode==`OUTB
|
xOpcode==`OUTW || xOpcode==`OUTH || xOpcode==`OUTC || xOpcode==`OUTB
|
;
|
;
|
wire m1IsIO =
|
wire m1IsIO =
|
m1IsIn ||
|
m1IsIn ||
|
m1Opcode==`OUTW || m1Opcode==`OUTH || m1Opcode==`OUTC || m1Opcode==`OUTB
|
m1Opcode==`OUTW || m1Opcode==`OUTH || m1Opcode==`OUTC || m1Opcode==`OUTB
|
;
|
;
|
wire m2IsLoad =
|
wire m2IsLoad =
|
m2Opcode==`LW || m2Opcode==`LH || m2Opcode==`LB || m2Opcode==`LC || m2Opcode==`LWR ||
|
m2Opcode==`LW || m2Opcode==`LH || m2Opcode==`LB || m2Opcode==`LC || m2Opcode==`LWR ||
|
m2Opcode==`LHU || m2Opcode==`LBU || m2Opcode==`LCU
|
m2Opcode==`LHU || m2Opcode==`LBU || m2Opcode==`LCU || m2Opcode==`LM ||
|
|
m2Opcode==`LF || m2Opcode==`LFD
|
;
|
;
|
wire m2IsStore =
|
|
m2Opcode==`SW || m2Opcode==`SWC || m2Opcode==`SH || m2Opcode==`SC || m2Opcode==`SB;
|
|
|
|
wire xIsFPLoo = xOpcode==`FPLOO;
|
wire xIsFPLoo = xOpcode==`FPLOO;
|
|
|
wire xneedBus = xIsIO;
|
wire xneedBus = xIsIO;
|
wire m1needBus = (m1IsLoad & !m1IsCacheElement) || m1IsStore || m1IsIO;
|
wire m1needBus = (m1IsLoad & !m1IsCacheElement) || m1IsStore || m1IsIO;
|
| Line 1412... |
Line 1415... |
wire StallR = (((xIsLoad||xIsIn) && ((xRt==dRa)||(xRt==dRb)||(xRt==dRt))) || xIsSWC) ||
|
wire StallR = (((xIsLoad||xIsIn) && ((xRt==dRa)||(xRt==dRb)||(xRt==dRt))) || xIsSWC) ||
|
(((m1IsLoad||m1IsIn) && ((m1Rt==dRa)||(m1Rt==dRb)||(m1Rt==dRt)))) ||
|
(((m1IsLoad||m1IsIn) && ((m1Rt==dRa)||(m1Rt==dRb)||(m1Rt==dRt)))) ||
|
(((m2IsLoad) && ((m2Rt==dRa)||(m2Rt==dRb)||(m2Rt==dRt))))
|
(((m2IsLoad) && ((m2Rt==dRa)||(m2Rt==dRb)||(m2Rt==dRt))))
|
;
|
;
|
wire StallX = xneedBus & (m1needBus|m2needBus|icaccess|dcaccess);
|
wire StallX = xneedBus & (m1needBus|m2needBus|icaccess|dcaccess);
|
wire StallM1 = m1needBus & (m2needBus|icaccess|dcaccess);
|
wire StallM1 = (m1needBus & (m2needBus|icaccess|dcaccess)) ||
|
|
( m1IsLoad & m1IsCacheElement & m2IsStore) // wait for a preceding store to complete
|
|
;
|
wire StallM2 = icaccess|dcaccess;
|
wire StallM2 = icaccess|dcaccess;
|
|
|
wire advanceT = !resetA;
|
wire advanceT = !resetA;
|
wire advanceW = advanceT;
|
wire advanceW = advanceT;
|
wire advanceM2 = advanceW &&
|
wire advanceM2 = advanceW &&
|
| Line 1441... |
Line 1446... |
wire triggerDCacheLoad = (m1IsLoad & m1IsCacheElement & !dhit) && // there is a miss
|
wire triggerDCacheLoad = (m1IsLoad & m1IsCacheElement & !dhit) && // there is a miss
|
!(icaccess | dcaccess) && // caches are not active
|
!(icaccess | dcaccess) && // caches are not active
|
m2Opcode==`NOPI // and the pipeline is free of memory-ops
|
m2Opcode==`NOPI // and the pipeline is free of memory-ops
|
;
|
;
|
// Since IMM is "sticky" we have to check for it.
|
// Since IMM is "sticky" we have to check for it.
|
wire triggerICacheLoad = (ICacheAct ? !ihit : !ibufrdy) && !triggerDCacheLoad && // There is a miss
|
wire triggerICacheLoad1 = ICacheAct && !ihit && !triggerDCacheLoad && // There is a miss
|
!(icaccess | dcaccess) && // caches are not active
|
!(icaccess | dcaccess) && // caches are not active
|
(dOpcode==`NOPI || dOpcode[6:4]==`IMM) && // and the pipeline is flushed
|
(dOpcode==`NOPI || dOpcode[6:4]==`IMM) && // and the pipeline is flushed
|
(xOpcode==`NOPI || xOpcode[6:4]==`IMM) &&
|
(xOpcode==`NOPI || xOpcode[6:4]==`IMM) &&
|
m1Opcode==`NOPI &&
|
m1Opcode==`NOPI &&
|
m2Opcode==`NOPI
|
m2Opcode==`NOPI
|
;
|
;
|
|
wire triggerICacheLoad2 = (!ICacheAct && !ibufrdy) && !triggerDCacheLoad && // There is a miss
|
|
!(icaccess | dcaccess) // caches are not active
|
|
;
|
|
wire triggerICacheLoad = triggerICacheLoad1 | triggerICacheLoad2;
|
|
|
wire EXexception_pending = ovr_error || dbz_error || priv_violation || xOpcode==`TRAPcci || xOpcode==`TRAPcc;
|
wire EXexception_pending = ovr_error || dbz_error || priv_violation || xOpcode==`TRAPcci || xOpcode==`TRAPcc;
|
`ifdef TLB
|
`ifdef TLB
|
wire M1exception_pending = advanceM1 & (m1IsLoad|m1IsStore) & DTLBMiss;
|
wire M1exception_pending = advanceM1 & (m1IsLoad|m1IsStore) & DTLBMiss;
|
`else
|
`else
|
wire M1exception_pending = 1'b0;
|
wire M1exception_pending = 1'b0;
|
`endif
|
`endif
|
wire exception_pending = EXexception_pending | M1exception_pending;
|
wire exception_pending = EXexception_pending | M1exception_pending;
|
|
|
wire xWillLoadStore = (xIsLoad||xIsStore) & advanceX;
|
|
wire stallCacheLoad = xWillLoadStore;
|
|
|
|
reg prev_nmi,nmi_edge;
|
reg prev_nmi,nmi_edge;
|
|
|
|
always @(dOpcode or dIR)
|
|
begin
|
|
ndIR <= dIR;
|
|
if ((dOpcode==`LM || dOpcode==`SM) && dIR[31:0]!=32'd0) begin
|
|
$display("LM/SM %h",dIR[31:0]);
|
|
if (dIR[0])
|
|
ndIR[0] <= 1'b0;
|
|
else if (dIR[1])
|
|
ndIR[1] <= 1'b0;
|
|
else if (dIR[2])
|
|
ndIR[2] <= 1'b0;
|
|
else if (dIR[3])
|
|
ndIR[3] <= 1'b0;
|
|
else if (dIR[4])
|
|
ndIR[4] <= 1'b0;
|
|
else if (dIR[5])
|
|
ndIR[5] <= 1'b0;
|
|
else if (dIR[6])
|
|
ndIR[6] <= 1'b0;
|
|
else if (dIR[7])
|
|
ndIR[7] <= 1'b0;
|
|
else if (dIR[8])
|
|
ndIR[8] <= 1'b0;
|
|
else if (dIR[9])
|
|
ndIR[9] <= 1'b0;
|
|
else if (dIR[10])
|
|
ndIR[10] <= 1'b0;
|
|
else if (dIR[11])
|
|
ndIR[11] <= 1'b0;
|
|
else if (dIR[12])
|
|
ndIR[12] <= 1'b0;
|
|
else if (dIR[13])
|
|
ndIR[13] <= 1'b0;
|
|
else if (dIR[14])
|
|
ndIR[14] <= 1'b0;
|
|
else if (dIR[15])
|
|
ndIR[15] <= 1'b0;
|
|
else if (dIR[16])
|
|
ndIR[16] <= 1'b0;
|
|
else if (dIR[17])
|
|
ndIR[17] <= 1'b0;
|
|
else if (dIR[18])
|
|
ndIR[18] <= 1'b0;
|
|
else if (dIR[19])
|
|
ndIR[19] <= 1'b0;
|
|
else if (dIR[20])
|
|
ndIR[20] <= 1'b0;
|
|
else if (dIR[21])
|
|
ndIR[21] <= 1'b0;
|
|
else if (dIR[22])
|
|
ndIR[22] <= 1'b0;
|
|
else if (dIR[23])
|
|
ndIR[23] <= 1'b0;
|
|
else if (dIR[24])
|
|
ndIR[24] <= 1'b0;
|
|
else if (dIR[25])
|
|
ndIR[25] <= 1'b0;
|
|
else if (dIR[26])
|
|
ndIR[26] <= 1'b0;
|
|
else if (dIR[27])
|
|
ndIR[27] <= 1'b0;
|
|
else if (dIR[28])
|
|
ndIR[28] <= 1'b0;
|
|
else if (dIR[29])
|
|
ndIR[29] <= 1'b0;
|
|
else if (dIR[30])
|
|
ndIR[30] <= 1'b0;
|
|
else
|
|
ndIR[31] <= 1'b0;
|
|
end
|
|
end
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// Register file.
|
// Register file.
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
|
|
| Line 1498... |
Line 1576... |
);
|
);
|
|
|
|
|
reg m1clkoff,m2clkoff,m3clkoff,m4clkoff,wclkoff;
|
reg m1clkoff,m2clkoff,m3clkoff,m4clkoff,wclkoff;
|
reg dFip,xFip,m1Fip,m2Fip,m3Fip,m4Fip,wFip;
|
reg dFip,xFip,m1Fip,m2Fip,m3Fip,m4Fip,wFip;
|
|
reg cyc1;
|
|
|
|
reg [63:0] nxt_c;
|
|
always @(dRc or xData or m1Data or m2Data or wData or tData or rfoc)
|
|
casex(dRc)
|
|
9'bxxxx00000: nxt_c <= 64'd0;
|
|
xRt: nxt_c <= xData;
|
|
m1Rt: nxt_c <= m1Data;
|
|
m2Rt: nxt_c <= m2Data;
|
|
wRt: nxt_c <= wData;
|
|
tRt: nxt_c <= tData;
|
|
default: nxt_c <= rfoc;
|
|
endcase
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if (rst_i) begin
|
if (rst_i) begin
|
bte_o <= 2'b00;
|
bte_o <= 2'b00;
|
cti_o <= 3'b000;
|
cti_o <= 3'b000;
|
| Line 1571... |
Line 1662... |
resetA <= 1'b1;
|
resetA <= 1'b1;
|
mutex_gate <= 64'h0;
|
mutex_gate <= 64'h0;
|
`ifndef BRANCH_PREDICTION_SIMPLE
|
`ifndef BRANCH_PREDICTION_SIMPLE
|
gbl_branch_hist <= 3'b000;
|
gbl_branch_hist <= 3'b000;
|
`endif
|
`endif
|
|
dcache_on <= 1'b0;
|
ICacheOn <= 1'b0;
|
ICacheOn <= 1'b0;
|
ibuftag <= 64'h0;
|
ibuftag0 <= 64'h0;
|
|
ibuftag1 <= 64'h0;
|
m1IsCacheElement <= 1'b0;
|
m1IsCacheElement <= 1'b0;
|
dtinit <= 1'b1;
|
dtinit <= 1'b1;
|
`ifdef RAS_PREDICTION
|
`ifdef RAS_PREDICTION
|
ras_sp <= 6'd63;
|
ras_sp <= 6'd63;
|
`endif
|
`endif
|
|
im <= 1'b1;
|
|
im1 <= 1'b1;
|
end
|
end
|
else begin
|
else begin
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// Initialize program counters
|
// Initialize program counters
|
| Line 1608... |
Line 1703... |
prev_nmi <= nmi_i;
|
prev_nmi <= nmi_i;
|
if (!prev_nmi & nmi_i)
|
if (!prev_nmi & nmi_i)
|
nmi_edge <= 1'b1;
|
nmi_edge <= 1'b1;
|
|
|
|
|
|
`ifdef ADDRESS_RESERVATION
|
// A store by any device in the system to a reserved address blcok
|
// A store by any device in the system to a reserved address blcok
|
// clears the reservation.
|
// clears the reservation.
|
|
|
if (sys_adv && sys_adr[63:5]==resv_address)
|
if (sys_adv && sys_adr[63:5]==resv_address)
|
resv_address <= 59'd0;
|
resv_address <= 59'd0;
|
|
`endif
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// TRAILER:
|
// TRAILER:
|
// - placeholder to allow the use of synchronous register
|
// - placeholder to allow the use of synchronous register
|
// memory
|
// memory
|
| Line 1684... |
Line 1781... |
m2clkoff <= 1'b0;
|
m2clkoff <= 1'b0;
|
m2pc <= 64'd0;
|
m2pc <= 64'd0;
|
m2extype <= `EX_NON;
|
m2extype <= `EX_NON;
|
if (m2extype==`EX_NON) begin
|
if (m2extype==`EX_NON) begin
|
case(m2Opcode)
|
case(m2Opcode)
|
`SH,`SC,`SB,`SW,`SWC:
|
`SH,`SC,`SB,`SW,`SWC,`SM,`SF,`SFD:
|
begin
|
begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
we_o <= 1'b0;
|
we_o <= 1'b0;
|
sel_o <= 4'h0;
|
sel_o <= 4'h0;
|
end
|
end
|
`LH:
|
`LH,`LF:
|
begin
|
begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
wData <= sel_o[7] ? {{32{dat_i[63]}},dat_i[63:32]}:{{32{dat_i[31]}},dat_i[31: 0]};
|
wData <= sel_o[7] ? {{32{dat_i[63]}},dat_i[63:32]}:{{32{dat_i[31]}},dat_i[31: 0]};
|
end
|
end
|
`LW,`LWR:
|
`LW,`LWR,`LM,`LFD:
|
begin
|
begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
wData <= dat_i;
|
wData <= dat_i;
|
| Line 1940... |
Line 2037... |
we_o <= 1'b0;
|
we_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
end
|
end
|
|
|
`LW:
|
`LW,`LM,`LFD:
|
if (!m1IsCacheElement) begin
|
if (!m1IsCacheElement) begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
sel_o <= 8'hFF;
|
sel_o <= 8'hFF;
|
adr_o <= {pea[63:3],3'b000};
|
adr_o <= {pea[63:3],3'b000};
|
| Line 1952... |
Line 2049... |
end
|
end
|
else if (dhit) begin
|
else if (dhit) begin
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
m2Data <= cdat;
|
m2Data <= cdat;
|
end
|
end
|
|
`ifdef ADDRESS_RESERVATION
|
`LWR:
|
`LWR:
|
if (!m1IsCacheElement) begin
|
if (!m1IsCacheElement) begin
|
rsv_o <= 1'b1;
|
rsv_o <= 1'b1;
|
resv_address <= pea[63:5];
|
resv_address <= pea[63:5];
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
| Line 1969... |
Line 2066... |
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
m2Data <= cdat;
|
m2Data <= cdat;
|
rsv_o <= 1'b1;
|
rsv_o <= 1'b1;
|
resv_address <= pea[63:5];
|
resv_address <= pea[63:5];
|
end
|
end
|
|
`endif
|
`LH:
|
`LH,`LF:
|
if (!m1IsCacheElement) begin
|
if (!m1IsCacheElement) begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
sel_o <= pea[2] ? 8'b11110000 : 8'b00001111;
|
sel_o <= pea[2] ? 8'b11110000 : 8'b00001111;
|
adr_o <= {pea[63:2],2'b00};
|
adr_o <= {pea[63:2],2'b00};
|
| Line 2016... |
Line 2113... |
endcase
|
endcase
|
adr_o <= {pea[63:1],1'b0};
|
adr_o <= {pea[63:1],1'b0};
|
m2Addr <= {pea[63:1],1'b0};
|
m2Addr <= {pea[63:1],1'b0};
|
end
|
end
|
else if (dhit) begin
|
else if (dhit) begin
|
|
$display("dhit=1, cdat=%h",cdat);
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
case(pea[2:1])
|
case(pea[2:1])
|
2'd0: m2Data <= {{48{cdat[15]}},cdat[15:0]};
|
2'd0: m2Data <= {{48{cdat[15]}},cdat[15:0]};
|
2'd1: m2Data <= {{48{cdat[31]}},cdat[31:16]};
|
2'd1: m2Data <= {{48{cdat[31]}},cdat[31:16]};
|
2'd2: m2Data <= {{48{cdat[47]}},cdat[47:32]};
|
2'd2: m2Data <= {{48{cdat[47]}},cdat[47:32]};
|
| Line 2111... |
Line 2209... |
3'b110: m2Data <= {56'd0,cdat[55:48]};
|
3'b110: m2Data <= {56'd0,cdat[55:48]};
|
3'b111: m2Data <= {56'd0,cdat[63:56]};
|
3'b111: m2Data <= {56'd0,cdat[63:56]};
|
endcase
|
endcase
|
end
|
end
|
|
|
`SW:
|
`SW,`SM,`SFD:
|
begin
|
begin
|
|
$display("SW/SM");
|
m2Addr <= {pea[63:3],3'b000};
|
m2Addr <= {pea[63:3],3'b000};
|
wrhit <= dhit;
|
wrhit <= dhit;
|
`ifdef TLB
|
`ifdef TLB
|
if (!m1UnmappedDataArea & !q[3])
|
if (!m1UnmappedDataArea & !q[3])
|
ITLBD[{q[2:0],pea[15:13]}] <= 1'b1;
|
ITLBD[{q[2:0],pea[15:13]}] <= 1'b1;
|
`endif
|
`endif
|
|
`ifdef ADDRESS_RESERVATION
|
if (resv_address==pea[63:5])
|
if (resv_address==pea[63:5])
|
resv_address <= 59'd0;
|
resv_address <= 59'd0;
|
|
`endif
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
we_o <= 1'b1;
|
sel_o <= 8'hFF;
|
sel_o <= 8'hFF;
|
adr_o <= {pea[63:3],3'b000};
|
adr_o <= {pea[63:3],3'b000};
|
dat_o <= m1Data;
|
dat_o <= m1Data;
|
end
|
end
|
|
|
`SH:
|
`SH,`SF:
|
begin
|
begin
|
wrhit <= dhit;
|
wrhit <= dhit;
|
m2Addr <= {pea[63:2],2'b00};
|
m2Addr <= {pea[63:2],2'b00};
|
`ifdef TLB
|
`ifdef TLB
|
if (!m1UnmappedDataArea & !q[3])
|
if (!m1UnmappedDataArea & !q[3])
|
ITLBD[{q[2:0],pea[15:13]}] <= 1'b1;
|
ITLBD[{q[2:0],pea[15:13]}] <= 1'b1;
|
`endif
|
`endif
|
|
`ifdef ADDRESS_RESERVATION
|
if (resv_address==pea[63:5])
|
if (resv_address==pea[63:5])
|
resv_address <= 59'd0;
|
resv_address <= 59'd0;
|
|
`endif
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
we_o <= 1'b1;
|
sel_o <= pea[2] ? 8'b11110000 : 8'b00001111;
|
sel_o <= pea[2] ? 8'b11110000 : 8'b00001111;
|
adr_o <= {pea[63:2],2'b00};
|
adr_o <= {pea[63:2],2'b00};
|
| Line 2156... |
Line 2259... |
m2Addr <= {pea[63:2],2'b00};
|
m2Addr <= {pea[63:2],2'b00};
|
`ifdef TLB
|
`ifdef TLB
|
if (!m1UnmappedDataArea & !q[3])
|
if (!m1UnmappedDataArea & !q[3])
|
ITLBD[{q[2:0],pea[15:13]}] <= 1'b1;
|
ITLBD[{q[2:0],pea[15:13]}] <= 1'b1;
|
`endif
|
`endif
|
|
`ifdef ADDRESS_RESERVATION
|
if (resv_address==pea[63:5])
|
if (resv_address==pea[63:5])
|
resv_address <= 59'd0;
|
resv_address <= 59'd0;
|
|
`endif
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
we_o <= 1'b1;
|
case(pea[2:1])
|
case(pea[2:1])
|
2'b00: sel_o <= 8'b00000011;
|
2'b00: sel_o <= 8'b00000011;
|
| Line 2175... |
Line 2280... |
|
|
`SB:
|
`SB:
|
begin
|
begin
|
wrhit <= dhit;
|
wrhit <= dhit;
|
m2Addr <= {pea[63:2],2'b00};
|
m2Addr <= {pea[63:2],2'b00};
|
|
`ifdef ADDRESS_RESERVATION
|
if (resv_address==pea[63:5])
|
if (resv_address==pea[63:5])
|
resv_address <= 59'd0;
|
resv_address <= 59'd0;
|
|
`endif
|
`ifdef TLB
|
`ifdef TLB
|
if (!m1UnmappedDataArea & !q[3])
|
if (!m1UnmappedDataArea & !q[3])
|
ITLBD[{q[2:0],pea[15:13]}] <= 1'b1;
|
ITLBD[{q[2:0],pea[15:13]}] <= 1'b1;
|
`endif
|
`endif
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
| Line 2198... |
Line 2305... |
endcase
|
endcase
|
adr_o <= {pea[63:2],2'b00};
|
adr_o <= {pea[63:2],2'b00};
|
dat_o <= {8{m1Data[7:0]}};
|
dat_o <= {8{m1Data[7:0]}};
|
end
|
end
|
|
|
|
`ifdef ADDRESS_RESERVATION
|
`SWC:
|
`SWC:
|
begin
|
begin
|
rsf <= 1'b0;
|
rsf <= 1'b0;
|
if (resv_address==pea[63:5]) begin
|
if (resv_address==pea[63:5]) begin
|
`ifdef TLB
|
`ifdef TLB
|
| Line 2220... |
Line 2328... |
rsf <= 1'b1;
|
rsf <= 1'b1;
|
end
|
end
|
else
|
else
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
end
|
end
|
|
`endif
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
| Line 2263... |
Line 2372... |
`MISC:
|
`MISC:
|
case(xFunc)
|
case(xFunc)
|
`WAIT: m1clkoff <= 1'b1;
|
`WAIT: m1clkoff <= 1'b1;
|
`ICACHE_ON: ICacheOn <= 1'b1;
|
`ICACHE_ON: ICacheOn <= 1'b1;
|
`ICACHE_OFF: ICacheOn <= 1'b0;
|
`ICACHE_OFF: ICacheOn <= 1'b0;
|
|
`DCACHE_ON: dcache_on <= 1'b1;
|
|
`DCACHE_OFF: dcache_on <= 1'b0;
|
`ifdef TLB
|
`ifdef TLB
|
`TLBP: ea <= TLBVirtPage;
|
`TLBP: ea <= TLBVirtPage;
|
`TLBR,`TLBWI:
|
`TLBR,`TLBWI:
|
begin
|
begin
|
i <= {Index[2:0],TLBVirtPage[15:13]};
|
i <= {Index[2:0],TLBVirtPage[15:13]};
|
| Line 2301... |
Line 2412... |
`ASID: ASID <= a[7:0];
|
`ASID: ASID <= a[7:0];
|
`EPC: EPC <= a;
|
`EPC: EPC <= a;
|
`TBA: TBA <= {a[63:12],12'h000};
|
`TBA: TBA <= {a[63:12],12'h000};
|
`AXC: AXC <= a[3:0];
|
`AXC: AXC <= a[3:0];
|
`NON_ICACHE_SEG: nonICacheSeg <= a[63:32];
|
`NON_ICACHE_SEG: nonICacheSeg <= a[63:32];
|
|
`FPCR: rm <= a[31:30];
|
|
`IPC: IPC <= a;
|
default: ;
|
default: ;
|
endcase
|
endcase
|
`OMG: mutex_gate[a[5:0]] <= 1'b1;
|
`OMG: mutex_gate[a[5:0]] <= 1'b1;
|
`CMG: mutex_gate[a[5:0]] <= 1'b0;
|
`CMG: mutex_gate[a[5:0]] <= 1'b0;
|
`OMGI: mutex_gate[xIR[12:7]] <= 1'b1;
|
`OMGI: mutex_gate[xIR[12:7]] <= 1'b1;
|
| Line 2402... |
Line 2515... |
3'b111: sel_o <= 8'b10000000;
|
3'b111: sel_o <= 8'b10000000;
|
endcase
|
endcase
|
adr_o <= xData;
|
adr_o <= xData;
|
dat_o <= {8{b[7:0]}};
|
dat_o <= {8{b[7:0]}};
|
end
|
end
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LWR,`SW,`SH,`SC,`SB,`SWC:
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LWR,`LF,`LFD,`LM,
|
|
`SW,`SH,`SC,`SB,`SWC,`SF,`SFD,`SM:
|
begin
|
begin
|
m1Data <= b;
|
m1Data <= b;
|
ea <= xData;
|
ea <= xData;
|
end
|
end
|
`MEMNDX:
|
`MEMNDX:
|
| Line 2437... |
Line 2551... |
if (advanceR) begin
|
if (advanceR) begin
|
xAXC <= dAXC;
|
xAXC <= dAXC;
|
xhwxtype <= dhwxtype;
|
xhwxtype <= dhwxtype;
|
xFip <= dFip;
|
xFip <= dFip;
|
xextype <= dextype;
|
xextype <= dextype;
|
|
if (dOpcode==`R && dFunc==`MYST)
|
|
xIR <= nxt_c;
|
|
else
|
xIR <= dIR;
|
xIR <= dIR;
|
xpc <= dpc;
|
xpc <= dpc;
|
xpcv <= dpcv;
|
xpcv <= dpcv;
|
xbranch_taken <= dbranch_taken;
|
xbranch_taken <= dbranch_taken;
|
dbranch_taken <= 1'b0;
|
dbranch_taken <= 1'b0;
|
dextype <= `EX_NON;
|
dextype <= `EX_NON;
|
if (dOpcode[6:4]!=`IMM) // IMM is "sticky"
|
if (dOpcode[6:4]!=`IMM && dOpcode!=`LM && dOpcode!=`SM) // IMM is "sticky"
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
dRa <= 9'd0;
|
dRa <= 9'd0;
|
dRb <= 9'd0;
|
dRb <= 9'd0;
|
|
|
// Result forward muxes
|
// Result forward muxes
|
| Line 2472... |
Line 2589... |
if (dOpcode==`SHFTI)
|
if (dOpcode==`SHFTI)
|
case(dFunc)
|
case(dFunc)
|
`RORI: b <= {58'd0,~dIR[24:19]+6'd1};
|
`RORI: b <= {58'd0,~dIR[24:19]+6'd1};
|
default: b <= {58'd0,dIR[24:19]};
|
default: b <= {58'd0,dIR[24:19]};
|
endcase
|
endcase
|
casex(dRc)
|
c <= nxt_c;
|
9'bxxxx00000: c <= 64'd0;
|
|
xRt: c <= xData;
|
|
m1Rt: c <= m1Data;
|
|
m2Rt: c <= m2Data;
|
|
wRt: c <= wData;
|
|
tRt: c <= tData;
|
|
default: c <= rfoc;
|
|
endcase
|
|
|
|
// Set the target register
|
// Set the target register
|
casex(dOpcode)
|
casex(dOpcode)
|
|
`R:
|
|
case(dFunc)
|
|
`MYST: xRt <= {dAXC,dIR[19:15]};
|
|
default: xRt <= {dAXC,dIR[29:25]};
|
|
endcase
|
`SETLO: xRt <= {dAXC,dIR[36:32]};
|
`SETLO: xRt <= {dAXC,dIR[36:32]};
|
`SETHI: xRt <= {dAXC,dIR[36:32]};
|
`SETHI: xRt <= {dAXC,dIR[36:32]};
|
`RR: xRt <= {dAXC,dIR[24:20]};
|
`RR: xRt <= {dAXC,dIR[24:20]};
|
`BTRI: xRt <= 9'd0;
|
`BTRI: xRt <= 9'd0;
|
`BTRR: xRt <= 9'd0;
|
`BTRR:
|
|
case(dIR[4:0])
|
|
`LOOP: xRt <= {AXC,dIR[29:25]};
|
|
default: xRt <= 9'd0;
|
|
endcase
|
`TRAPcc: xRt <= 9'd0;
|
`TRAPcc: xRt <= 9'd0;
|
`TRAPcci: xRt <= 9'd0;
|
`TRAPcci: xRt <= 9'd0;
|
`JMP: xRt <= 9'd00;
|
`JMP: xRt <= 9'd00;
|
`CALL: xRt <= {dAXC,5'd31};
|
`CALL: xRt <= {dAXC,5'd31};
|
`RET: xRt <= {dAXC,dIR[24:20]};
|
`RET: xRt <= {dAXC,dIR[24:20]};
|
`MEMNDX:
|
`MEMNDX:
|
case(dFunc)
|
case(dFunc)
|
`SW,`SH,`SC,`SB,`OUTW,`OUTH,`OUTC,`OUTB:
|
`SW,`SH,`SC,`SB,`SF,`SFD,
|
|
`OUTW,`OUTH,`OUTC,`OUTB:
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
default: xRt <= {dAXC,dIR[24:20]};
|
default: xRt <= {dAXC,dIR[24:20]};
|
endcase
|
endcase
|
`SW,`SH,`SC,`SB,`OUTW,`OUTH,`OUTC,`OUTB:
|
`SW,`SH,`SC,`SB,`SF,`SFD, // but not SWC!
|
|
`OUTW,`OUTH,`OUTC,`OUTB:
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
`NOPI: xRt <= 9'd0;
|
`NOPI: xRt <= 9'd0;
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
|
`SM: xRt <= 9'd0;
|
|
`LM:
|
|
casex(dIR[30:0])
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1: xRt <= {AXC,5'd1};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxx10: xRt <= {AXC,5'd2};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxx100: xRt <= {AXC,5'd3};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxx1000: xRt <= {AXC,5'd4};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxx10000: xRt <= {AXC,5'd5};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxx100000: xRt <= {AXC,5'd6};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxx1000000: xRt <= {AXC,5'd7};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxx10000000: xRt <= {AXC,5'd8};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxx100000000: xRt <= {AXC,5'd9};
|
|
31'bxxxxxxxxxxxxxxxxxxxxx1000000000: xRt <= {AXC,5'd10};
|
|
31'bxxxxxxxxxxxxxxxxxxxx10000000000: xRt <= {AXC,5'd11};
|
|
31'bxxxxxxxxxxxxxxxxxxx100000000000: xRt <= {AXC,5'd12};
|
|
31'bxxxxxxxxxxxxxxxxxx1000000000000: xRt <= {AXC,5'd13};
|
|
31'bxxxxxxxxxxxxxxxxx10000000000000: xRt <= {AXC,5'd14};
|
|
31'bxxxxxxxxxxxxxxxx100000000000000: xRt <= {AXC,5'd15};
|
|
31'bxxxxxxxxxxxxxxx1000000000000000: xRt <= {AXC,5'd16};
|
|
31'bxxxxxxxxxxxxxx10000000000000000: xRt <= {AXC,5'd17};
|
|
31'bxxxxxxxxxxxxx100000000000000000: xRt <= {AXC,5'd18};
|
|
31'bxxxxxxxxxxxx1000000000000000000: xRt <= {AXC,5'd19};
|
|
31'bxxxxxxxxxxx10000000000000000000: xRt <= {AXC,5'd20};
|
|
31'bxxxxxxxxxx100000000000000000000: xRt <= {AXC,5'd21};
|
|
31'bxxxxxxxxx1000000000000000000000: xRt <= {AXC,5'd22};
|
|
31'bxxxxxxxx10000000000000000000000: xRt <= {AXC,5'd23};
|
|
31'bxxxxxxx100000000000000000000000: xRt <= {AXC,5'd24};
|
|
31'bxxxxxx1000000000000000000000000: xRt <= {AXC,5'd25};
|
|
31'bxxxxx10000000000000000000000000: xRt <= {AXC,5'd26};
|
|
31'bxxxx100000000000000000000000000: xRt <= {AXC,5'd27};
|
|
31'bxxx1000000000000000000000000000: xRt <= {AXC,5'd28};
|
|
31'bxx10000000000000000000000000000: xRt <= {AXC,5'd29};
|
|
31'bx100000000000000000000000000000: xRt <= {AXC,5'd30};
|
|
31'b1000000000000000000000000000000: xRt <= {AXC,5'd31};
|
|
default: xRt <= 9'h000;
|
|
endcase
|
|
|
default: xRt <= {dAXC,dIR[29:25]};
|
default: xRt <= {dAXC,dIR[29:25]};
|
endcase
|
endcase
|
if (dOpcode[6:4]==`IMM)
|
if (dOpcode[6:4]==`IMM)
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
|
|
| Line 2522... |
Line 2679... |
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
imm <= {{46{dIR[17]}},dIR[17:0]};
|
imm <= {{46{dIR[17]}},dIR[17:0]};
|
`ANDI: imm <= {39'h7FFFFFFFFF,dIR[24:0]};
|
`ANDI: imm <= {39'h7FFFFFFFFF,dIR[24:0]};
|
`ORI: imm <= {39'h0000000000,dIR[24:0]};
|
`ORI: imm <= {39'h0000000000,dIR[24:0]};
|
`XORI: imm <= {39'h0000000000,dIR[24:0]};
|
`XORI: imm <= {39'h0000000000,dIR[24:0]};
|
`RET: imm <= {44'h00000000000,dIR[19:0]};
|
`RET: imm <= {41'h00000000,dIR[19:0],3'b000};
|
`MEMNDX: imm <= {{51{dIR[19]}},dIR[19:7]};
|
`MEMNDX: imm <= {{51{dIR[19]}},dIR[19:7]};
|
default: imm <= {{39{dIR[24]}},dIR[24:0]};
|
default: imm <= {{39{dIR[24]}},dIR[24:0]};
|
endcase
|
endcase
|
case(dOpcode)
|
case(dOpcode)
|
|
|
| Line 2535... |
Line 2692... |
`SEI: im <= 1'b1;
|
`SEI: im <= 1'b1;
|
`CLI: im <= 1'b0;
|
`CLI: im <= 1'b0;
|
endcase
|
endcase
|
endcase
|
endcase
|
|
|
|
if ((dOpcode==`SM || dOpcode==`LM) && dIR[31:0]!=32'd0)
|
|
dIR <= ndIR;
|
end
|
end
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// IFETCH:
|
// IFETCH:
|
// - check for external hardware interrupt
|
// - check for external hardware interrupt
|
| Line 2547... |
Line 2706... |
// - set special register defaults for some instructions
|
// - set special register defaults for some instructions
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (advanceI) begin
|
if (advanceI) begin
|
dAXC <= AXC;
|
dAXC <= AXC;
|
dextype <= `EX_NON;
|
dextype <= `EX_NON;
|
if (nmi_edge & !StatusHWI) begin
|
if (nmi_edge & !StatusHWI & !im1) begin
|
$display("*****************");
|
$display("*****************");
|
$display("NMI edge detected");
|
$display("NMI edge detected");
|
$display("*****************");
|
$display("*****************");
|
StatusHWI <= 1'b1;
|
StatusHWI <= 1'b1;
|
nmi_edge <= 1'b0;
|
nmi_edge <= 1'b0;
|
dhwxtype <= 2'b01;
|
dhwxtype <= 2'b01;
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
dextype <= `EX_NMI;
|
dextype <= `EX_NMI;
|
end
|
end
|
else if (irq_i & !im & !StatusHWI) begin
|
else if (irq_i & !im & !StatusHWI & !im1) begin
|
im <= 1'b1;
|
im <= 1'b1;
|
StatusHWI <= 1'b1;
|
StatusHWI <= 1'b1;
|
dhwxtype <= 2'b10;
|
dhwxtype <= 2'b10;
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
dextype <= `EX_IRQ;
|
dextype <= `EX_IRQ;
|
| Line 2574... |
Line 2733... |
`ifdef TLB
|
`ifdef TLB
|
else if (ITLBMiss)
|
else if (ITLBMiss)
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
`endif
|
`endif
|
else begin
|
else begin
|
|
if ((iOpcode==`SM || iOpcode==`LM) && insn[31:0]!=32'd0)
|
|
im1 <= 1'b1;
|
|
else
|
|
im1 <= 1'b0;
|
|
if ((iOpcode==`SM || iOpcode==`LM) && insn[31:0]==32'd0) begin
|
|
dIR <= `NOP_INSN;
|
|
pc <= fnIncPC(pc);
|
|
end
|
|
else
|
dIR <= insn;
|
dIR <= insn;
|
`include "insn_dumpsc.v"
|
`include "insn_dumpsc.v"
|
end
|
end
|
nopI <= 1'b0;
|
nopI <= 1'b0;
|
if (dOpcode[6:4]!=`IMM) begin
|
if (dOpcode[6:4]!=`IMM) begin
|
dpc <= pc;
|
dpc <= pc;
|
dpcv <= 1'b1;
|
dpcv <= 1'b1;
|
end
|
end
|
|
dRb <= {AXC,insn[29:25]};
|
|
dRc <= {AXC,insn[24:20]};
|
casex(iOpcode)
|
casex(iOpcode)
|
`SETLO: dRa <= {AXC,insn[36:32]};
|
`SETLO: dRa <= {AXC,insn[36:32]};
|
`SETHI: dRa <= {AXC,insn[36:32]};
|
`SETHI: dRa <= {AXC,insn[36:32]};
|
|
`SM,`LM:
|
|
begin
|
|
dRa <= {AXC,1'b1,insn[34:31]};
|
|
casex(insn[30:0])
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1: dRb <= {AXC,5'd1};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxx10: dRb <= {AXC,5'd2};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxx100: dRb <= {AXC,5'd3};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxx1000: dRb <= {AXC,5'd4};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxx10000: dRb <= {AXC,5'd5};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxx100000: dRb <= {AXC,5'd6};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxxx1000000: dRb <= {AXC,5'd7};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxxx10000000: dRb <= {AXC,5'd8};
|
|
31'bxxxxxxxxxxxxxxxxxxxxxx100000000: dRb <= {AXC,5'd9};
|
|
31'bxxxxxxxxxxxxxxxxxxxxx1000000000: dRb <= {AXC,5'd10};
|
|
31'bxxxxxxxxxxxxxxxxxxxx10000000000: dRb <= {AXC,5'd11};
|
|
31'bxxxxxxxxxxxxxxxxxxx100000000000: dRb <= {AXC,5'd12};
|
|
31'bxxxxxxxxxxxxxxxxxx1000000000000: dRb <= {AXC,5'd13};
|
|
31'bxxxxxxxxxxxxxxxxx10000000000000: dRb <= {AXC,5'd14};
|
|
31'bxxxxxxxxxxxxxxxx100000000000000: dRb <= {AXC,5'd15};
|
|
31'bxxxxxxxxxxxxxxx1000000000000000: dRb <= {AXC,5'd16};
|
|
31'bxxxxxxxxxxxxxx10000000000000000: dRb <= {AXC,5'd17};
|
|
31'bxxxxxxxxxxxxx100000000000000000: dRb <= {AXC,5'd18};
|
|
31'bxxxxxxxxxxxx1000000000000000000: dRb <= {AXC,5'd19};
|
|
31'bxxxxxxxxxxx10000000000000000000: dRb <= {AXC,5'd20};
|
|
31'bxxxxxxxxxx100000000000000000000: dRb <= {AXC,5'd21};
|
|
31'bxxxxxxxxx1000000000000000000000: dRb <= {AXC,5'd22};
|
|
31'bxxxxxxxx10000000000000000000000: dRb <= {AXC,5'd23};
|
|
31'bxxxxxxx100000000000000000000000: dRb <= {AXC,5'd24};
|
|
31'bxxxxxx1000000000000000000000000: dRb <= {AXC,5'd25};
|
|
31'bxxxxx10000000000000000000000000: dRb <= {AXC,5'd26};
|
|
31'bxxxx100000000000000000000000000: dRb <= {AXC,5'd27};
|
|
31'bxxx1000000000000000000000000000: dRb <= {AXC,5'd28};
|
|
31'bxx10000000000000000000000000000: dRb <= {AXC,5'd29};
|
|
31'bx100000000000000000000000000000: dRb <= {AXC,5'd30};
|
|
31'b1000000000000000000000000000000: dRb <= {AXC,5'd31};
|
|
default: dRb <= {AXC,5'd0};
|
|
endcase
|
|
end
|
default: dRa <= {AXC,insn[34:30]};
|
default: dRa <= {AXC,insn[34:30]};
|
endcase
|
endcase
|
dRb <= {AXC,insn[29:25]};
|
|
dRc <= {AXC,insn[24:20]};
|
|
`ifdef TLB
|
`ifdef TLB
|
if (ITLBMiss) begin
|
if (ITLBMiss) begin
|
$display("TLB miss on instruction fetch.");
|
$display("TLB miss on instruction fetch.");
|
CauseCode <= `EX_TLBI;
|
CauseCode <= `EX_TLBI;
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
| Line 2602... |
Line 2808... |
end
|
end
|
else
|
else
|
`endif
|
`endif
|
begin
|
begin
|
dbranch_taken <= 1'b0;
|
dbranch_taken <= 1'b0;
|
|
if ((iOpcode==`LM || iOpcode==`SM) && insn[31:0]!=32'd0)
|
|
;
|
|
else begin
|
pc <= fnIncPC(pc);
|
pc <= fnIncPC(pc);
|
|
end
|
case(iOpcode)
|
case(iOpcode)
|
`MISC:
|
`MISC:
|
case(iFunc)
|
case(iFunc)
|
`FIP: dFip <= 1'b1;
|
`FIP: dFip <= 1'b1;
|
default: ;
|
default: ;
|
| Line 2637... |
Line 2847... |
dbranch_taken <= 1'b1;
|
dbranch_taken <= 1'b1;
|
pc <= jmp_tgt;
|
pc <= jmp_tgt;
|
end
|
end
|
`BTRR:
|
`BTRR:
|
case(insn[4:0])
|
case(insn[4:0])
|
`BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BAND,`BOR,`BNR:
|
`BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BAND,`BOR,`BRA,`BNR,`BRN,`LOOP:
|
if (predict_taken) begin
|
if (predict_taken) begin
|
// $display("Taking predicted branch: %h",{pc[63:4] + {{42{insn[24]}},insn[24:7]},insn[6:5],2'b00});
|
// $display("Taking predicted branch: %h",{pc[63:4] + {{42{insn[24]}},insn[24:7]},insn[6:5],2'b00});
|
dbranch_taken <= 1'b1;
|
dbranch_taken <= 1'b1;
|
pc <= {pc[63:4] + {{42{insn[24]}},insn[24:7]},insn[6:5],2'b00};
|
pc <= {pc[63:4] + {{42{insn[24]}},insn[24:7]},insn[6:5],2'b00};
|
end
|
end
|
| Line 2706... |
Line 2916... |
`R:
|
`R:
|
case(xFunc)
|
case(xFunc)
|
`EXEC:
|
`EXEC:
|
begin
|
begin
|
pc <= fnIncPC(xpc);
|
pc <= fnIncPC(xpc);
|
|
dRa <= b[34:30];
|
|
dRb <= b[29:25];
|
|
dRc <= b[24:20];
|
dIR <= b;
|
dIR <= b;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
| Line 2717... |
Line 2930... |
default: ;
|
default: ;
|
endcase
|
endcase
|
`BTRR:
|
`BTRR:
|
case(xIR[4:0])
|
case(xIR[4:0])
|
// BEQ r1,r2,label
|
// BEQ r1,r2,label
|
`BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BAND,`BOR,`BNR:
|
`BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BAND,`BOR,`BNR,`LOOP,`BRA,`BRN:
|
if (!takb & xbranch_taken) begin
|
if (!takb & xbranch_taken) begin
|
$display("Taking mispredicted branch %h",fnIncPC(xpc));
|
$display("Taking mispredicted branch %h",fnIncPC(xpc));
|
pc <= fnIncPC(xpc);
|
pc <= fnIncPC(xpc);
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
| Line 3070... |
Line 3283... |
if (adr_o[3]==1'b0) begin
|
if (adr_o[3]==1'b0) begin
|
cti_o <= 3'b111; // Last cycle ahead
|
cti_o <= 3'b111; // Last cycle ahead
|
tmpbuf <= dat_i;
|
tmpbuf <= dat_i;
|
end
|
end
|
else begin
|
else begin
|
insnbuf <= {dat_i,tmpbuf};
|
if (tick[0]) begin
|
|
insnbuf0 <= {dat_i,tmpbuf};
|
|
ibuftag0 <= adr_o[63:4];
|
|
end
|
|
else begin
|
|
insnbuf1 <= {dat_i,tmpbuf};
|
|
ibuftag1 <= adr_o[63:4];
|
|
end
|
cti_o <= 3'b000; // back to non-burst mode
|
cti_o <= 3'b000; // back to non-burst mode
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
icaccess <= 1'b0;
|
icaccess <= 1'b0;
|
ibuftag <= adr_o[63:4];
|
|
cstate <= IDLE;
|
cstate <= IDLE;
|
end
|
end
|
end
|
end
|
|
|
DCACT:
|
DCACT:
|
