| Line 34... |
Line 34... |
`define TRAP_VECTOR 64'h0000_0000_0000_0000
|
`define TRAP_VECTOR 64'h0000_0000_0000_0000
|
|
|
`define TLBMissPage 52'hFFFF_FFFF_FFFF_F
|
`define TLBMissPage 52'hFFFF_FFFF_FFFF_F
|
`define ITLB_MissHandler 64'hFFFF_FFFF_FFFF_FFC0
|
`define ITLB_MissHandler 64'hFFFF_FFFF_FFFF_FFC0
|
`define DTLB_MissHandler 64'hFFFF_FFFF_FFFF_FFB0
|
`define DTLB_MissHandler 64'hFFFF_FFFF_FFFF_FFB0
|
|
`define BERR_VECTOR 64'hFFFF_FFFF_FFFF_FFA0
|
|
|
`define GEN_TRAP_OFFSET 13'h0200
|
`define GEN_TRAP_OFFSET 13'h0200
|
`define DBZ_TRAP_OFFSET 13'h0050
|
`define DBZ_TRAP_OFFSET 13'h0050
|
`define OFL_TRAP_OFFSET 13'h0070
|
`define OFL_TRAP_OFFSET 13'h0070
|
`define PRIV_OFFSET 13'h0080
|
`define PRIV_OFFSET 13'h0080
|
|
|
`define EX_NON 8'd0
|
`define EX_NON 9'd000
|
`define EX_RST 8'd1
|
`define EX_TRAP 9'd32 // Trap exception
|
`define EX_NMI 8'd2
|
`define EX_IRQ 9'd449 // interrupt
|
`define EX_IRQ 8'd3
|
`define EX_DBZ 9'd488 // divide by zero
|
`define EX_TRAP 8'd4
|
`define EX_OFL 9'd489 // overflow
|
`define EX_PRIV 8'd5 // priviledge violation
|
`define EX_PRIV 9'd496 // priviledge violation
|
`define EX_OFL 8'd16 // overflow
|
`define EX_TLBD 9'd506 // TLB exception - data
|
`define EX_DBZ 8'd17 // divide by zero
|
`define EX_TLBI 9'd507 // TLB exception - ifetch
|
`define EX_TLBI 8'd19 // TLB exception - ifetch
|
`define EX_DBERR 9'd508 // Bus Error - load or store or I/O
|
`define EX_TLBD 8'd20 // TLB exception - data
|
`define EX_IBERR 9'd509 // Bus Error - instruction fetch
|
|
`define EX_NMI 9'd510 // non-maskable interrupt
|
|
`define EX_RST 9'd511 // Reset
|
|
|
`define EXCEPT_Int 5'd00
|
`define EXCEPT_Int 5'd00
|
`define EXCEPT_Mod 5'd01 // TLB modification
|
`define EXCEPT_Mod 5'd01 // TLB modification
|
`define EXCEPT_TLBL 5'd02 // TLB exception - load or ifetch
|
`define EXCEPT_TLBL 5'd02 // TLB exception - load or ifetch
|
`define EXCEPT_TLBS 5'd03 // TLB exception - store
|
`define EXCEPT_TLBS 5'd03 // TLB exception - store
|
| Line 79... |
Line 82... |
`define ICACHE_ON 7'd10
|
`define ICACHE_ON 7'd10
|
`define ICACHE_OFF 7'd11
|
`define ICACHE_OFF 7'd11
|
`define DCACHE_ON 7'd12
|
`define DCACHE_ON 7'd12
|
`define DCACHE_OFF 7'd13
|
`define DCACHE_OFF 7'd13
|
`define FIP 7'd20
|
`define FIP 7'd20
|
|
`define SYSJMP 7'd22
|
|
`define SYSCALL 7'd23
|
`define IRET 7'd32
|
`define IRET 7'd32
|
`define ERET 7'd33
|
`define ERET 7'd33
|
`define WAIT 7'd40
|
`define WAIT 7'd40
|
`define TLBP 7'd49
|
`define TLBP 7'd49
|
`define TLBR 7'd50
|
`define TLBR 7'd50
|
| Line 438... |
Line 443... |
`define IMM 3'd7
|
`define IMM 3'd7
|
|
|
`define NOP_INSN 42'b1101111_000_00000000_00000000_00000000_00000000
|
`define NOP_INSN 42'b1101111_000_00000000_00000000_00000000_00000000
|
|
|
module Raptor64sc(rst_i, clk_i, nmi_i, irq_i, bte_o, cti_o, bl_o,
|
module Raptor64sc(rst_i, clk_i, nmi_i, irq_i, bte_o, cti_o, bl_o,
|
cyc_o, stb_o, ack_i, we_o, sel_o, rsv_o, adr_o, dat_i, dat_o, sys_adv, sys_adr
|
cyc_o, stb_o, ack_i, err_i, we_o, sel_o, rsv_o, adr_o, dat_i, dat_o, sys_adv, sys_adr
|
);
|
);
|
parameter IDLE = 5'd1;
|
parameter IDLE = 5'd1;
|
parameter ICACT = 5'd2;
|
parameter ICACT = 5'd2;
|
parameter ICACT0 = 5'd3;
|
parameter ICACT0 = 5'd3;
|
parameter ICACT1 = 5'd4;
|
parameter ICACT1 = 5'd4;
|
| Line 479... |
Line 484... |
output cyc_o;
|
output cyc_o;
|
reg cyc_o;
|
reg cyc_o;
|
output stb_o;
|
output stb_o;
|
reg stb_o;
|
reg stb_o;
|
input ack_i;
|
input ack_i;
|
|
input err_i;
|
output we_o;
|
output we_o;
|
reg we_o;
|
reg we_o;
|
output [7:0] sel_o;
|
output [7:0] sel_o;
|
reg [7:0] sel_o;
|
reg [7:0] sel_o;
|
output rsv_o;
|
output rsv_o;
|
| Line 499... |
Line 505... |
reg [5:0] fltctr;
|
reg [5:0] fltctr;
|
wire fltdone = fltctr==6'd0;
|
wire fltdone = fltctr==6'd0;
|
reg resetA;
|
reg resetA;
|
reg im,bu_im; // interrupt mask
|
reg im,bu_im; // interrupt mask
|
reg im1; // temporary interrupt mask for LM/SM
|
reg im1; // temporary interrupt mask for LM/SM
|
|
reg [1:0] vtno; // vector table number
|
reg [1:0] rm; // fp rounding mode
|
reg [1:0] rm; // fp rounding mode
|
reg FXE; // fp exception enable
|
reg FXE; // fp exception enable
|
wire KernelMode;
|
wire KernelMode;
|
wire [31:0] sr = {bu_im,15'd0,im,1'b0,KernelMode,FXE,12'b0};
|
wire [31:0] sr = {bu_im,15'd0,im,1'b0,KernelMode,FXE,vtno,10'b0};
|
reg [41:0] dIR;
|
reg [41:0] dIR;
|
reg [41:0] ndIR;
|
reg [41:0] ndIR;
|
wire [6:0] dOpcode = dIR[41:35];
|
wire [6:0] dOpcode = dIR[41:35];
|
reg [41:0] xIR;
|
reg [41:0] xIR;
|
reg [63:0] pc;
|
reg [63:0] pc;
|
| Line 562... |
Line 569... |
reg [7:0] CauseCode;
|
reg [7:0] CauseCode;
|
reg [7:0] ASID; // address space identifier (process ID)
|
reg [7:0] ASID; // address space identifier (process ID)
|
integer n;
|
integer n;
|
reg [63:13] BadVAddr;
|
reg [63:13] BadVAddr;
|
reg [63:13] PageTableAddr;
|
reg [63:13] PageTableAddr;
|
|
reg [63:0] errorAddress;
|
|
|
function [63:0] fnIncPC;
|
function [63:0] fnIncPC;
|
input [63:0] fpc;
|
input [63:0] fpc;
|
begin
|
begin
|
case(fpc[3:2])
|
case(fpc[3:2])
|
| Line 759... |
Line 767... |
//wire isEncrypted = ppc[63:32]==encryptedArea;
|
//wire isEncrypted = ppc[63:32]==encryptedArea;
|
wire ICacheAct = ICacheOn & isICached;
|
wire ICacheAct = ICacheOn & isICached;
|
reg [41:0] insn1;
|
reg [41:0] insn1;
|
reg [41:0] insnkey;
|
reg [41:0] insnkey;
|
|
|
|
// SYSCALL 509
|
|
wire [127:0] bevect = 128'b00_00000000_00000000_00000000_11111110_10010111__00_00000000_00000000_00000000_11111110_10010111__00_00000000_00000000_00000000_11111110_10010111;
|
|
|
Raptor64_icache_ram u1
|
Raptor64_icache_ram u1
|
(
|
(
|
.clka(clk), // input clka
|
.clka(clk), // input clka
|
.wea(icaccess & ack_i), // input [0 : 0] wea
|
.wea(icaccess & (ack_i|err_i)), // input [0 : 0] wea
|
.addra(adr_o[12:3]), // input [9 : 0] addra
|
.addra(adr_o[12:3]), // input [9 : 0] addra
|
.dina(dat_i), // input [63 : 0] dina
|
.dina(err_i ? (adr_o[3] ? bevect[127:64] : bevect[63:0]) : dat_i), // input [63 : 0] dina
|
.clkb(~clk), // input clkb
|
.clkb(~clk), // input clkb
|
.addrb(pc[12:4]), // input [8 : 0] addrb
|
.addrb(pc[12:4]), // input [8 : 0] addrb
|
.doutb(insnbundle) // output [127 : 0] doutb
|
.doutb(insnbundle) // output [127 : 0] doutb
|
);
|
);
|
|
|
| Line 881... |
Line 892... |
reg prev_ihit;
|
reg prev_ihit;
|
reg rsf;
|
reg rsf;
|
reg [63:5] resv_address;
|
reg [63:5] resv_address;
|
reg dirqf,rirqf,m1irqf,m2irqf,wirqf,tirqf;
|
reg dirqf,rirqf,m1irqf,m2irqf,wirqf,tirqf;
|
reg xirqf;
|
reg xirqf;
|
reg [7:0] dextype,m1extype,m2extype,wextype,textype,exception_type;
|
reg [8:0] dextype,m1extype,m2extype,wextype,textype,exception_type;
|
reg [7:0] xextype;
|
reg [8:0] xextype;
|
|
reg wLdPC,m2LdPC;
|
wire advanceX_edge;
|
wire advanceX_edge;
|
reg takb;
|
reg takb;
|
|
|
|
|
|
|
| Line 965... |
Line 977... |
|
|
wire [63:0] fpZLOut;
|
wire [63:0] fpZLOut;
|
wire [63:0] fpLooOut;
|
wire [63:0] fpLooOut;
|
wire fpLooDone;
|
wire fpLooDone;
|
|
|
|
/*
|
|
fpZLUnit #(64) u30
|
|
(
|
|
.op(xFunc[5:0]),
|
|
.a(a),
|
|
.b(b), // for fcmp
|
|
.o(fpZLOut),
|
|
.nanx()
|
|
);
|
|
|
fpZLUnit #(64) u30
|
fpLOOUnit #(64) u31
|
(
|
(
|
.op(xFunc[5:0]),
|
.clk(clk),
|
.a(a),
|
.ce(1'b1),
|
.b(b), // for fcmp
|
.rm(rm),
|
.o(fpZLOut),
|
.op(xFunc[5:0]),
|
.nanx()
|
.a(a),
|
);
|
.o(fpLooOut),
|
|
.done(fpLooDone)
|
fpLOOUnit #(64) u31
|
);
|
(
|
|
.clk(clk),
|
|
.ce(1'b1),
|
|
.rm(rm),
|
|
.op(xFunc[5:0]),
|
|
.a(a),
|
|
.o(fpLooOut),
|
|
.done(fpLooDone)
|
|
);
|
|
|
|
|
|
|
*/
|
wire dcmp_result;
|
wire dcmp_result;
|
wire [63:0] daddsub_result;
|
wire [63:0] daddsub_result;
|
wire [63:0] ddiv_result;
|
wire [63:0] ddiv_result;
|
wire [63:0] dmul_result;
|
wire [63:0] dmul_result;
|
wire [63:0] i2f_result;
|
wire [63:0] i2f_result;
|
| Line 1409... |
Line 1421... |
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Datapath (ALU) operations.
|
// Datapath (ALU) operations.
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
wire [6:0] cntlzo,cntloo;
|
wire [6:0] cntlzo,cntloo;
|
cntlz64 u12 ( .i(a), .o(cntlzo) );
|
cntlz64 u12 (.clk(clk), .i(a), .o(cntlzo) );
|
cntlo64 u13 ( .i(a), .o(cntloo) );
|
cntlo64 u13 (.clk(clk), .i(a), .o(cntloo) );
|
|
|
reg [1:0] shftop;
|
reg [1:0] shftop;
|
wire [63:0] shfto;
|
wire [63:0] shfto;
|
reg [63:0] masko;
|
reg [63:0] masko;
|
//wire shl = (xOpcode==`RR && xFunc==`SHL) || (xOpcode==`SHFTI && xFunc==`SHLI);
|
//wire shl = (xOpcode==`RR && xFunc==`SHL) || (xOpcode==`SHFTI && xFunc==`SHLI);
|
| Line 1465... |
Line 1477... |
shfto or masko or bcdaddo or bcdsubo or fpLooOut or fpZLOut
|
shfto or masko or bcdaddo or bcdsubo or fpLooOut or fpZLOut
|
`ifdef TLB
|
`ifdef TLB
|
or Wired or Index or Random or TLBPhysPage0 or TLBPhysPage1 or TLBVirtPage or TLBASID or
|
or Wired or Index or Random or TLBPhysPage0 or TLBPhysPage1 or TLBVirtPage or TLBASID or
|
PageTableAddr or BadVAddr or ASID or TLBPageMask
|
PageTableAddr or BadVAddr or ASID or TLBPageMask
|
`endif
|
`endif
|
or ASID or EPC or mutex_gate or IPC or CauseCode or TBA or xAXC or nonICacheSeg or rm
|
or ASID or EPC or mutex_gate or IPC or CauseCode or TBA or xAXC or nonICacheSeg or rm or
|
|
rando
|
)
|
)
|
casex(xOpcode)
|
casex(xOpcode)
|
`R:
|
`R:
|
casex(xFunc)
|
casex(xFunc)
|
`COM: xData = ~a;
|
`COM: xData = ~a;
|
| Line 1688... |
Line 1701... |
wire xIsSqrt = xOpcode==`R && xFunc==`SQRT;
|
wire xIsSqrt = xOpcode==`R && xFunc==`SQRT;
|
wire xIsMult = (xOpcode==`RR && (xFunc==`MULU || xFunc==`MULS)) ||
|
wire xIsMult = (xOpcode==`RR && (xFunc==`MULU || xFunc==`MULS)) ||
|
xOpcode==`MULSI || xOpcode==`MULUI;
|
xOpcode==`MULSI || xOpcode==`MULUI;
|
wire xIsDiv = (xOpcode==`RR && (xFunc==`DIVU || xFunc==`DIVS)) ||
|
wire xIsDiv = (xOpcode==`RR && (xFunc==`DIVU || xFunc==`DIVS)) ||
|
xOpcode==`DIVSI || xOpcode==`DIVUI;
|
xOpcode==`DIVSI || xOpcode==`DIVUI;
|
|
wire xIsCnt = xOpcode==`R && (xFunc==`CTLZ || xFunc==`CTLO || xFunc==`CTPOP);
|
|
reg m1IsCnt,m2IsCnt;
|
|
|
wire xIsLoad =
|
wire xIsLoad =
|
xOpcode==`LW || xOpcode==`LH || xOpcode==`LB || xOpcode==`LWR ||
|
xOpcode==`LW || xOpcode==`LH || xOpcode==`LB || xOpcode==`LWR ||
|
xOpcode==`LHU || xOpcode==`LBU ||
|
xOpcode==`LHU || xOpcode==`LBU ||
|
xOpcode==`LC || xOpcode==`LCU || xOpcode==`LM ||
|
xOpcode==`LC || xOpcode==`LCU || xOpcode==`LM ||
|
| Line 1701... |
Line 1716... |
xFunc6==`LWX || xFunc6==`LHX || xFunc6==`LBX || xFunc6==`LWRX ||
|
xFunc6==`LWX || xFunc6==`LHX || xFunc6==`LBX || xFunc6==`LWRX ||
|
xFunc6==`LHUX || xFunc6==`LBUX ||
|
xFunc6==`LHUX || xFunc6==`LBUX ||
|
xFunc6==`LCX || xFunc6==`LCUX ||
|
xFunc6==`LCX || xFunc6==`LCUX ||
|
xFunc6==`LFX || xFunc6==`LFDX || xFunc6==`LPX ||
|
xFunc6==`LFX || xFunc6==`LFDX || xFunc6==`LPX ||
|
xFunc6==`LSHX || xFunc6==`LSWX
|
xFunc6==`LSHX || xFunc6==`LSWX
|
))
|
)) ||
|
|
(xOpcode==`MISC && (xFunc==`SYSJMP || xFunc==`SYSCALL))
|
;
|
;
|
|
|
wire xIsStore =
|
wire xIsStore =
|
xOpcode==`SW || xOpcode==`SH || xOpcode==`SB || xOpcode==`SC || xOpcode==`SWC || xOpcode==`SM ||
|
xOpcode==`SW || xOpcode==`SH || xOpcode==`SB || xOpcode==`SC || xOpcode==`SWC || xOpcode==`SM ||
|
xOpcode==`SF || xOpcode==`SFD || xOpcode==`SP || xOpcode==`SFP || xOpcode==`SFDP ||
|
xOpcode==`SF || xOpcode==`SFD || xOpcode==`SP || xOpcode==`SFP || xOpcode==`SFDP ||
|
xOpcode==`SSH || xOpcode==`SSW ||
|
xOpcode==`SSH || xOpcode==`SSW ||
|
(xOpcode==`MEMNDX && (
|
(xOpcode==`MEMNDX && (
|
| Line 1743... |
Line 1760... |
wire m1needBus = (m1IsLoad & !m1IsCacheElement) || m1IsStore || m1IsIO;
|
wire m1needBus = (m1IsLoad & !m1IsCacheElement) || m1IsStore || m1IsIO;
|
wire m2needBus = (m2IsLoad | m2IsStore);
|
wire m2needBus = (m2IsLoad | m2IsStore);
|
|
|
// Stall on SWC allows rsf flag to be loaded for the next instruction
|
// Stall on SWC allows rsf flag to be loaded for the next instruction
|
// Currently stalls on load of R0, but doesn't need to.
|
// Currently stalls on load of R0, but doesn't need to.
|
wire StallR = (((xIsLoad||xIsIn) && ((xRt==dRa)||(xRt==dRb)||(xRt==dRt))) || xIsSWC) ||
|
wire StallR = (((xIsLoad||xIsIn||xIsCnt) && ((xRt==dRa)||(xRt==dRb)||(xRt==dRt))) || xIsSWC) ||
|
(((m1IsLoad||m1IsIn) && ((m1Rt==dRa)||(m1Rt==dRb)||(m1Rt==dRt)))) ||
|
(((m1IsLoad||m1IsIn||m1IsCnt) && ((m1Rt==dRa)||(m1Rt==dRb)||(m1Rt==dRt)))) ||
|
(((m2IsLoad) && ((m2Rt==dRa)||(m2Rt==dRb)||(m2Rt==dRt))))
|
(((m2IsLoad||m2IsCnt) && ((m2Rt==dRa)||(m2Rt==dRb)||(m2Rt==dRt))))
|
;
|
;
|
wire StallX = xneedBus & (m1needBus|m2needBus|icaccess|dcaccess);
|
wire StallX = xneedBus & (m1needBus|m2needBus|icaccess|dcaccess);
|
wire StallM1 = (m1needBus & (m2needBus|icaccess|dcaccess)) ||
|
wire StallM1 = (m1needBus & (m2needBus|icaccess|dcaccess)) ||
|
( m1IsLoad & m1IsCacheElement & (m2IsStore|wIsStore)) // wait for a preceding store to complete
|
( m1IsLoad & m1IsCacheElement & (m2IsStore|wIsStore)) // wait for a preceding store to complete
|
;
|
;
|
wire StallM2 = icaccess|dcaccess;
|
wire StallM2 = icaccess|dcaccess;
|
|
|
wire advanceT = !resetA;
|
wire advanceT = !resetA;
|
wire advanceW = advanceT;
|
wire advanceW = advanceT;
|
wire advanceM2 = advanceW &&
|
wire advanceM2 = advanceW &&
|
((m2IsLoad || m2IsStore) ? ack_i : 1'b1) &&
|
((m2IsLoad || m2IsStore) ? (ack_i|err_i) : 1'b1) &&
|
!StallM2
|
!StallM2
|
;
|
;
|
wire advanceM1 = advanceM2 &
|
wire advanceM1 = advanceM2 &
|
(m1IsIO ? ack_i : 1'b1) &
|
(m1IsIO ? (ack_i|err_i) : 1'b1) &
|
((m1IsLoad & m1IsCacheElement) ? dhit : 1'b1) &
|
((m1IsLoad & m1IsCacheElement) ? dhit : 1'b1) &
|
!StallM1
|
!StallM1
|
;
|
;
|
wire advanceX = advanceM1 & (
|
wire advanceX = advanceM1 & (
|
xIsSqrt ? sqrt_done :
|
xIsSqrt ? sqrt_done :
|
| Line 1979... |
Line 1996... |
m2Rt <= 9'd0;
|
m2Rt <= 9'd0;
|
tData <= 64'd0;
|
tData <= 64'd0;
|
wData <= 64'd0;
|
wData <= 64'd0;
|
m1Data <= 64'd0;
|
m1Data <= 64'd0;
|
m2Data <= 64'd0;
|
m2Data <= 64'd0;
|
|
m2LdPC <= 1'b0;
|
|
wLdPC <= 1'b0;
|
m1IsLoad <= 1'b0;
|
m1IsLoad <= 1'b0;
|
m2IsLoad <= 1'b0;
|
m2IsLoad <= 1'b0;
|
m1IsStore <= 1'b0;
|
m1IsStore <= 1'b0;
|
m2IsStore <= 1'b0;
|
m2IsStore <= 1'b0;
|
wIsStore <= 1'b0;
|
wIsStore <= 1'b0;
|
| Line 2105... |
Line 2124... |
// - jump to exception handler routine (below)
|
// - jump to exception handler routine (below)
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (advanceW) begin
|
if (advanceW) begin
|
textype <= wextype;
|
textype <= wextype;
|
wextype <= `EX_NON;
|
wextype <= `EX_NON;
|
|
if (wextype==`EX_IRQ)
|
|
$display("wextype=IRQ");
|
tRt <= wRt;
|
tRt <= wRt;
|
tData <= wData;
|
tData <= wData;
|
if (wRt!=5'd0)
|
if (wRt!=5'd0)
|
$display("Writing regfile[%d:%d] with %h", wRt[8:5],wRt[4:0], wData);
|
$display("Writing regfile[%d:%d] with %h", wRt[8:5],wRt[4:0], wData);
|
case(wOpcode)
|
case(wOpcode)
|
| Line 2124... |
Line 2145... |
endcase
|
endcase
|
wRt <= 9'd0;
|
wRt <= 9'd0;
|
wData <= 64'd0;
|
wData <= 64'd0;
|
wOpcode <= `NOPI;
|
wOpcode <= `NOPI;
|
wIsStore <= 1'b0;
|
wIsStore <= 1'b0;
|
|
wLdPC <= 1'b0;
|
if (|whwxtype) begin
|
if (|whwxtype) begin
|
dhwxtype <= 2'b00;
|
dhwxtype <= 2'b00;
|
xhwxtype <= 2'b00;
|
xhwxtype <= 2'b00;
|
m1hwxtype <= 2'b00;
|
m1hwxtype <= 2'b00;
|
m2hwxtype <= 2'b00;
|
m2hwxtype <= 2'b00;
|
| Line 2154... |
Line 2176... |
if (advanceM2) begin
|
if (advanceM2) begin
|
wIsStore <= m2IsStore;
|
wIsStore <= m2IsStore;
|
wOpcode <= m2Opcode;
|
wOpcode <= m2Opcode;
|
wData <= m2Data;
|
wData <= m2Data;
|
whwxtype <= m2hwxtype;
|
whwxtype <= m2hwxtype;
|
wextype <= m2extype;
|
wextype <= (m2IsLoad|m2IsStore)&err_i ? `EX_DBERR : m2extype;
|
|
if (m2extype==`EX_IRQ)
|
|
$display("m2extype=IRQ");
|
wRt <= m2Rt;
|
wRt <= m2Rt;
|
wpc <= m2pc;
|
wpc <= m2pc;
|
wpcv <= m2pcv;
|
wpcv <= m2pcv;
|
wclkoff <= m2clkoff;
|
wclkoff <= m2clkoff;
|
wFip <= m2Fip;
|
wFip <= m2Fip;
|
|
wLdPC <= m2LdPC;
|
|
|
m2Rt <= 9'd0;
|
m2Rt <= 9'd0;
|
m2Opcode <= `NOPI;
|
m2Opcode <= `NOPI;
|
m2IsLoad <= 1'b0;
|
m2IsLoad <= 1'b0;
|
m2IsStore <= 1'b0;
|
m2IsStore <= 1'b0;
|
|
m2IsCnt <= 1'b0;
|
m2Func <= 7'd0;
|
m2Func <= 7'd0;
|
m2Addr <= 64'd0;
|
m2Addr <= 64'd0;
|
m2Data <= 64'd0;
|
m2Data <= 64'd0;
|
m2clkoff <= 1'b0;
|
m2clkoff <= 1'b0;
|
m2pc <= 64'd0;
|
m2pc <= 64'd0;
|
m2extype <= `EX_NON;
|
m2extype <= `EX_NON;
|
|
m2LdPC <= 1'b0;
|
|
if ((m2IsLoad|m2IsStore)&err_i)
|
|
errorAddress <= adr_o;
|
if (m2extype==`EX_NON) begin
|
if (m2extype==`EX_NON) begin
|
case(m2Opcode)
|
case(m2Opcode)
|
|
`MISC:
|
|
if (m2Func==`SYSJMP || m2Func==`SYSCALL)
|
|
begin
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
sel_o <= 8'h00;
|
|
wData <= {dat_i[63:2],2'b00};
|
|
end
|
`SH,`SC,`SB,`SW,`SWC,`SM,`SF,`SFD,`SSH,`SSW,`SP,`SFP,`SFDP:
|
`SH,`SC,`SB,`SW,`SWC,`SM,`SF,`SFD,`SSH,`SSW,`SP,`SFP,`SFDP:
|
begin
|
begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
we_o <= 1'b0;
|
we_o <= 1'b0;
|
| Line 2279... |
Line 2316... |
// to cause the pipeline to advance as if a NOPs were
|
// to cause the pipeline to advance as if a NOPs were
|
// present.
|
// present.
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (advanceM1) begin
|
if (advanceM1) begin
|
m2Opcode <= m1Opcode;
|
m2Opcode <= m1Opcode;
|
|
m2Func <= m1Func;
|
m2IsLoad <= m1IsLoad;
|
m2IsLoad <= m1IsLoad;
|
m2IsStore <= m1IsStore;
|
m2IsStore <= m1IsStore;
|
|
m2IsCnt <= m1IsCnt;
|
m2Func <= m1Func;
|
m2Func <= m1Func;
|
m2Addr <= pea;
|
m2Addr <= pea;
|
m2Data <= m1Data;
|
m2Data <= m1Data;
|
m2hwxtype <= m1hwxtype;
|
m2hwxtype <= m1hwxtype;
|
m2extype <= m1extype;
|
m2extype <= m1IsIO & err_i ? `EX_DBERR : m1extype;
|
|
if (m1extype==`EX_IRQ)
|
|
$display("m1extype=IRQ");
|
m2Rt <= m1Rt;
|
m2Rt <= m1Rt;
|
m2pc <= m1pc;
|
m2pc <= m1pc;
|
m2pcv <= m1pcv;
|
m2pcv <= m1pcv;
|
m2clkoff <= m1clkoff;
|
m2clkoff <= m1clkoff;
|
m2Fip <= m1Fip;
|
m2Fip <= m1Fip;
|
|
|
m1Rt <= 9'd0;
|
m1Rt <= 9'd0;
|
m1IsLoad <= 1'b0;
|
m1IsLoad <= 1'b0;
|
m1IsStore <= 1'b0;
|
m1IsStore <= 1'b0;
|
|
m1IsCnt <= 1'b0;
|
m1IsIO <= 1'b0;
|
m1IsIO <= 1'b0;
|
m1Opcode <= `NOPI;
|
m1Opcode <= `NOPI;
|
m1Func <= 7'd0;
|
m1Func <= 7'd0;
|
m1Data <= 64'd0;
|
m1Data <= 64'd0;
|
m1clkoff <= 1'b0;
|
m1clkoff <= 1'b0;
|
m1pc <= 64'd0;
|
m1pc <= 64'd0;
|
m1IsCacheElement <= 1'b0;
|
m1IsCacheElement <= 1'b0;
|
m1extype <= `EX_NON;
|
m1extype <= `EX_NON;
|
|
|
|
if (m1IsIO&err_i)
|
|
errorAddress <= adr_o;
|
|
|
if (m1extype == `EX_NON) begin
|
if (m1extype == `EX_NON) begin
|
case(m1Opcode)
|
case(m1Opcode)
|
`MISC:
|
`MISC:
|
case(m1Func)
|
case(m1Func)
|
|
`SYSJMP,`SYSCALL:
|
|
begin
|
|
m2LdPC <= 1'b1;
|
|
if (!m1IsCacheElement) begin
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
sel_o <= 8'hFF;
|
|
adr_o <= {pea[63:3],3'b000};
|
|
m2Addr <= {pea[63:3],3'b000};
|
|
end
|
|
else if (dhit) begin
|
|
m2IsLoad <= 1'b0;
|
|
m2Opcode <= `NOPI;
|
|
m2Data <= {cdat[63:2],2'b00};
|
|
end
|
|
end
|
`ifdef TLB
|
`ifdef TLB
|
`TLBP:
|
`TLBP:
|
begin
|
begin
|
Index[63] <= ~|DMatch;
|
Index[63] <= ~|DMatch;
|
end
|
end
|
| Line 2745... |
Line 2806... |
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (advanceX) begin
|
if (advanceX) begin
|
m1hwxtype <= xhwxtype;
|
m1hwxtype <= xhwxtype;
|
m1Fip <= xFip;
|
m1Fip <= xFip;
|
m1extype <= xextype;
|
m1extype <= xextype;
|
|
if (xextype==`EX_IRQ)
|
|
$display("xextype=IRQ");
|
m1IsLoad <= xIsLoad;
|
m1IsLoad <= xIsLoad;
|
m1IsStore <= xIsStore;
|
m1IsStore <= xIsStore;
|
|
m1IsCnt <= xIsCnt;
|
m1IsIO <= xIsIO;
|
m1IsIO <= xIsIO;
|
m1Opcode <= xOpcode;
|
m1Opcode <= xOpcode;
|
m1Func <= xFunc;
|
m1Func <= xFunc;
|
m1Rt <= xRt;
|
m1Rt <= xRt;
|
m1Data <= xData;
|
m1Data <= xData;
|
| Line 2796... |
Line 2860... |
m_z1 <= next_m_z1;
|
m_z1 <= next_m_z1;
|
m_z2 <= next_m_z2;
|
m_z2 <= next_m_z2;
|
m_w1 <= next_m_w1;
|
m_w1 <= next_m_w1;
|
m_w2 <= next_m_w2;
|
m_w2 <= next_m_w2;
|
end
|
end
|
|
`SYSJMP,`SYSCALL:
|
|
begin
|
|
ea <= {TBA[63:12],xIR[15:7],3'b000};
|
|
end
|
`ifdef TLB
|
`ifdef TLB
|
`TLBP: ea <= TLBVirtPage;
|
`TLBP: ea <= TLBVirtPage;
|
`TLBR,`TLBWI:
|
`TLBR,`TLBWI:
|
begin
|
begin
|
i <= {Index[2:0],TLBVirtPage[15:13]};
|
i <= {Index[2:0],TLBVirtPage[15:13]};
|
| Line 3051... |
Line 3119... |
if (advanceR) begin
|
if (advanceR) begin
|
xAXC <= dAXC;
|
xAXC <= dAXC;
|
xhwxtype <= dhwxtype;
|
xhwxtype <= dhwxtype;
|
xFip <= dFip;
|
xFip <= dFip;
|
xextype <= dextype;
|
xextype <= dextype;
|
|
if (dextype==`EX_IRQ)
|
|
$display("dextype=IRQ");
|
if (dOpcode==`R && dFunc==`MYST)
|
if (dOpcode==`R && dFunc==`MYST)
|
xIR <= nxt_c;
|
xIR <= nxt_c;
|
else
|
else
|
xIR <= dIR;
|
xIR <= dIR;
|
xpc <= dpc;
|
xpc <= dpc;
|
| Line 3067... |
Line 3137... |
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
dRa <= 9'd0;
|
dRa <= 9'd0;
|
dRb <= 9'd0;
|
dRb <= 9'd0;
|
|
|
a <= nxt_a;
|
a <= nxt_a;
|
// casex(dRb)
|
|
// 9'bxxxx00000: b <= 64'd0;
|
|
// xRt: b <= disRightShift ? -xData[5:0] : xData;
|
|
// m1Rt: b <= disRightShift ? -m1Data[5:0] : m1Data;
|
|
// m2Rt: b <= disRightShift ? -m2Data[5:0] : m2Data;
|
|
// wRt: b <= disRightShift ? -wData[5:0] : wData;
|
|
// tRt: b <= disRightShift ? -tData[5:0] : tData;
|
|
// default: b <= disRightShift ? -rfob[5:0] : rfob;
|
|
// endcase
|
|
b <= nxt_b;
|
b <= nxt_b;
|
if (dOpcode==`SHFTI)
|
if (dOpcode==`SHFTI)
|
b <= {58'd0,dIR[24:19]};
|
b <= {58'd0,dIR[24:19]};
|
// case(dFunc)
|
|
// `RORI: b <= {58'd0,~dIR[24:19]+6'd1};
|
|
// default: b <= {58'd0,dIR[24:19]};
|
|
// endcase
|
|
c <= nxt_c;
|
c <= nxt_c;
|
|
|
// Set the target register
|
// Set the target register
|
casex(dOpcode)
|
casex(dOpcode)
|
`R:
|
`R:
|
case(dFunc)
|
case(dFunc)
|
|
`MTSPR,`CMG,`CMGI,`EXEC:
|
|
xRt <= 9'd0;
|
`MYST: xRt <= {dAXC,dIR[19:15]};
|
`MYST: xRt <= {dAXC,dIR[19:15]};
|
default: xRt <= {dAXC,dIR[29:25]};
|
default: xRt <= {dAXC,dIR[29:25]};
|
endcase
|
endcase
|
`SETLO: xRt <= {dAXC,dIR[36:32]};
|
`SETLO: xRt <= {dAXC,dIR[36:32]};
|
`SETHI: xRt <= {dAXC,dIR[36:32]};
|
`SETHI: xRt <= {dAXC,dIR[36:32]};
|
`RR,`FP: xRt <= {dAXC,dIR[24:20]};
|
`RR,`FP: xRt <= {dAXC,dIR[24:20]};
|
`BTRI: xRt <= 9'd0;
|
`BTRI: xRt <= 9'd0;
|
`BTRR:
|
`BTRR:
|
case(dIR[4:0])
|
case(dIR[4:0])
|
`LOOP: xRt <= {AXC,dIR[29:25]};
|
`LOOP: xRt <= {dAXC,dIR[29:25]};
|
default: xRt <= 9'd0;
|
default: xRt <= 9'd0;
|
endcase
|
endcase
|
`TRAPcc: xRt <= 9'd0;
|
`TRAPcc: xRt <= 9'd0;
|
`TRAPcci: xRt <= 9'd0;
|
`TRAPcci: xRt <= 9'd0;
|
`JMP: xRt <= 9'd00;
|
`JMP: xRt <= 9'd00;
|
| Line 3123... |
Line 3182... |
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
`SM: xRt <= 9'd0;
|
`SM: xRt <= 9'd0;
|
`LM:
|
`LM:
|
casex(dIR[30:0])
|
casex(dIR[30:0])
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1: xRt <= {AXC,5'd1};
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1: xRt <= {dAXC,5'd1};
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxx10: xRt <= {AXC,5'd2};
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxx10: xRt <= {dAXC,5'd2};
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxx100: xRt <= {AXC,5'd3};
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxx100: xRt <= {dAXC,5'd3};
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxx1000: xRt <= {AXC,5'd4};
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxxx1000: xRt <= {dAXC,5'd4};
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxx10000: xRt <= {AXC,5'd5};
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxxx10000: xRt <= {dAXC,5'd5};
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxx100000: xRt <= {AXC,5'd6};
|
31'bxxxxxxxxxxxxxxxxxxxxxxxxx100000: xRt <= {dAXC,5'd6};
|
31'bxxxxxxxxxxxxxxxxxxxxxxxx1000000: xRt <= {AXC,5'd7};
|
31'bxxxxxxxxxxxxxxxxxxxxxxxx1000000: xRt <= {dAXC,5'd7};
|
31'bxxxxxxxxxxxxxxxxxxxxxxx10000000: xRt <= {AXC,5'd8};
|
31'bxxxxxxxxxxxxxxxxxxxxxxx10000000: xRt <= {dAXC,5'd8};
|
31'bxxxxxxxxxxxxxxxxxxxxxx100000000: xRt <= {AXC,5'd9};
|
31'bxxxxxxxxxxxxxxxxxxxxxx100000000: xRt <= {dAXC,5'd9};
|
31'bxxxxxxxxxxxxxxxxxxxxx1000000000: xRt <= {AXC,5'd10};
|
31'bxxxxxxxxxxxxxxxxxxxxx1000000000: xRt <= {dAXC,5'd10};
|
31'bxxxxxxxxxxxxxxxxxxxx10000000000: xRt <= {AXC,5'd11};
|
31'bxxxxxxxxxxxxxxxxxxxx10000000000: xRt <= {dAXC,5'd11};
|
31'bxxxxxxxxxxxxxxxxxxx100000000000: xRt <= {AXC,5'd12};
|
31'bxxxxxxxxxxxxxxxxxxx100000000000: xRt <= {dAXC,5'd12};
|
31'bxxxxxxxxxxxxxxxxxx1000000000000: xRt <= {AXC,5'd13};
|
31'bxxxxxxxxxxxxxxxxxx1000000000000: xRt <= {dAXC,5'd13};
|
31'bxxxxxxxxxxxxxxxxx10000000000000: xRt <= {AXC,5'd14};
|
31'bxxxxxxxxxxxxxxxxx10000000000000: xRt <= {dAXC,5'd14};
|
31'bxxxxxxxxxxxxxxxx100000000000000: xRt <= {AXC,5'd15};
|
31'bxxxxxxxxxxxxxxxx100000000000000: xRt <= {dAXC,5'd15};
|
31'bxxxxxxxxxxxxxxx1000000000000000: xRt <= {AXC,5'd16};
|
31'bxxxxxxxxxxxxxxx1000000000000000: xRt <= {dAXC,5'd16};
|
31'bxxxxxxxxxxxxxx10000000000000000: xRt <= {AXC,5'd17};
|
31'bxxxxxxxxxxxxxx10000000000000000: xRt <= {dAXC,5'd17};
|
31'bxxxxxxxxxxxxx100000000000000000: xRt <= {AXC,5'd18};
|
31'bxxxxxxxxxxxxx100000000000000000: xRt <= {dAXC,5'd18};
|
31'bxxxxxxxxxxxx1000000000000000000: xRt <= {AXC,5'd19};
|
31'bxxxxxxxxxxxx1000000000000000000: xRt <= {dAXC,5'd19};
|
31'bxxxxxxxxxxx10000000000000000000: xRt <= {AXC,5'd20};
|
31'bxxxxxxxxxxx10000000000000000000: xRt <= {dAXC,5'd20};
|
31'bxxxxxxxxxx100000000000000000000: xRt <= {AXC,5'd21};
|
31'bxxxxxxxxxx100000000000000000000: xRt <= {dAXC,5'd21};
|
31'bxxxxxxxxx1000000000000000000000: xRt <= {AXC,5'd22};
|
31'bxxxxxxxxx1000000000000000000000: xRt <= {dAXC,5'd22};
|
31'bxxxxxxxx10000000000000000000000: xRt <= {AXC,5'd23};
|
31'bxxxxxxxx10000000000000000000000: xRt <= {dAXC,5'd23};
|
31'bxxxxxxx100000000000000000000000: xRt <= {AXC,5'd24};
|
31'bxxxxxxx100000000000000000000000: xRt <= {dAXC,5'd24};
|
31'bxxxxxx1000000000000000000000000: xRt <= {AXC,5'd25};
|
31'bxxxxxx1000000000000000000000000: xRt <= {dAXC,5'd25};
|
31'bxxxxx10000000000000000000000000: xRt <= {AXC,5'd26};
|
31'bxxxxx10000000000000000000000000: xRt <= {dAXC,5'd26};
|
31'bxxxx100000000000000000000000000: xRt <= {AXC,5'd27};
|
31'bxxxx100000000000000000000000000: xRt <= {dAXC,5'd27};
|
31'bxxx1000000000000000000000000000: xRt <= {AXC,5'd28};
|
31'bxxx1000000000000000000000000000: xRt <= {dAXC,5'd28};
|
31'bxx10000000000000000000000000000: xRt <= {AXC,5'd29};
|
31'bxx10000000000000000000000000000: xRt <= {dAXC,5'd29};
|
31'bx100000000000000000000000000000: xRt <= {AXC,5'd30};
|
31'bx100000000000000000000000000000: xRt <= {dAXC,5'd30};
|
31'b1000000000000000000000000000000: xRt <= {AXC,5'd31};
|
31'b1000000000000000000000000000000: xRt <= {dAXC,5'd31};
|
default: xRt <= 9'h000;
|
default: xRt <= 9'h000;
|
endcase
|
endcase
|
|
|
default: xRt <= {dAXC,dIR[29:25]};
|
default: xRt <= {dAXC,dIR[29:25]};
|
endcase
|
endcase
|
| Line 3204... |
Line 3263... |
dhwxtype <= 2'b01;
|
dhwxtype <= 2'b01;
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
dextype <= `EX_NMI;
|
dextype <= `EX_NMI;
|
end
|
end
|
else if (irq_i & !im & !StatusHWI & !im1) begin
|
else if (irq_i & !im & !StatusHWI & !im1) begin
|
|
$display("*****************");
|
|
$display("IRQ detected");
|
|
$display("*****************");
|
bu_im <= 1'b0;
|
bu_im <= 1'b0;
|
im <= 1'b1;
|
im <= 1'b1;
|
StatusHWI <= 1'b1;
|
StatusHWI <= 1'b1;
|
dhwxtype <= 2'b10;
|
dhwxtype <= 2'b10;
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
| Line 3310... |
Line 3372... |
if ((iOpcode==`SP || iOpcode==`LP || iOpcode==`SFP || iOpcode==`LFP || iOpcode==`SFDP || iOpcode==`LFDP) && !insn[25])
|
if ((iOpcode==`SP || iOpcode==`LP || iOpcode==`SFP || iOpcode==`LFP || iOpcode==`SFDP || iOpcode==`LFDP) && !insn[25])
|
;
|
;
|
else if ((iOpcode==`LM || iOpcode==`SM) && insn[31:0]!=32'd0)
|
else if ((iOpcode==`LM || iOpcode==`SM) && insn[31:0]!=32'd0)
|
;
|
;
|
else begin
|
else begin
|
|
if (pc!=64'd3)
|
pc <= fnIncPC(pc);
|
pc <= fnIncPC(pc);
|
end
|
end
|
case(iOpcode)
|
case(iOpcode)
|
`MISC:
|
`MISC:
|
case(iFunc)
|
case(iFunc)
|
| Line 3368... |
Line 3431... |
if (predict_taken) begin
|
if (predict_taken) begin
|
dbranch_taken <= 1'b1;
|
dbranch_taken <= 1'b1;
|
pc <= {pc[63:4] + {{50{insn[29]}},insn[29:20]},insn[19:18],2'b00};
|
pc <= {pc[63:4] + {{50{insn[29]}},insn[29:20]},insn[19:18],2'b00};
|
end
|
end
|
end
|
end
|
`TRAPcc: if (predict_taken) begin pc <= {TBA[63:13],`GEN_TRAP_OFFSET}; dbranch_taken <= 1'b1; end
|
|
`TRAPcci: if (predict_taken) begin pc <= {TBA[63:13],`GEN_TRAP_OFFSET}; dbranch_taken <= 1'b1; end
|
|
default: ;
|
default: ;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
//`include "RPSTAGE.v"
|
//`include "RPSTAGE.v"
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// EXECUTE - part two:
|
// EXECUTE (EX')- part two:
|
// - override the default program counter increment for
|
// - override the default program counter increment for
|
// control flow instructions
|
// control flow instructions
|
// - NOP out the instructions following a branch in the
|
// - NOP out the instructions following a branch in the
|
// pipeline
|
// pipeline
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
| Line 3408... |
Line 3469... |
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
|
`SYSJMP:
|
|
begin
|
|
StatusEXL <= 1'b1;
|
|
pc <= 64'd3;
|
|
dIR <= `NOP_INSN;
|
|
xIR <= `NOP_INSN;
|
|
xRt <= 9'd0;
|
|
xpcv <= 1'b0;
|
|
dpcv <= 1'b0;
|
|
end
|
|
`SYSCALL:
|
|
begin
|
|
StatusEXL <= 1'b1;
|
|
EPC <= fnIncPC(xpc);
|
|
pc <= 64'd3;
|
|
dIR <= `NOP_INSN;
|
|
xIR <= `NOP_INSN;
|
|
xRt <= 9'd0;
|
|
xpcv <= 1'b0;
|
|
dpcv <= 1'b0;
|
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
`R:
|
`R:
|
case(xFunc)
|
case(xFunc)
|
`EXEC:
|
`EXEC:
|
| Line 3562... |
Line 3644... |
end
|
end
|
`TRAPcc,`TRAPcci:
|
`TRAPcc,`TRAPcci:
|
if (takb) begin
|
if (takb) begin
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
CauseCode <= `EX_TRAP;
|
CauseCode <= `EX_TRAP;
|
EPC <= xpc;
|
xextype <= `EX_TRAP;
|
if (!xbranch_taken) begin
|
pc <= 64'd3;
|
pc <= {TBA[63:13],`GEN_TRAP_OFFSET};
|
|
dIR <= `NOP_INSN;
|
|
xIR <= `NOP_INSN;
|
|
xRt <= 9'd0;
|
|
xpcv <= 1'b0;
|
|
dpcv <= 1'b0;
|
|
end
|
|
end
|
|
else begin
|
|
if (xbranch_taken) begin
|
|
// $display("Taking mispredicted branch %h",fnIncPC(xpc));
|
|
pc <= fnIncPC(xpc);
|
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
end
|
|
default: ;
|
default: ;
|
endcase
|
endcase
|
|
|
if (dbz_error) begin
|
if (dbz_error) begin
|
$display("Divide by zero error");
|
$display("Divide by zero error");
|
CauseCode <= `EX_DBZ;
|
CauseCode <= `EX_DBZ;
|
|
xextype <= `EX_DBZ;
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
EPC <= xpc;
|
pc <= 64'd3;
|
pc <= {TBA[63:13],`DBZ_TRAP_OFFSET};
|
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
else if (ovr_error) begin
|
else if (ovr_error) begin
|
$display("Overflow error");
|
$display("Overflow error");
|
CauseCode <= `EX_OFL;
|
CauseCode <= `EX_OFL;
|
|
xextype <= `EX_OFL;
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
EPC <= xpc;
|
pc <= 64'd3;
|
pc <= {TBA[63:13],`OFL_TRAP_OFFSET};
|
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
else if (priv_violation) begin
|
else if (priv_violation) begin
|
$display("Priviledge violation");
|
$display("Priviledge violation");
|
CauseCode <= `EX_PRIV;
|
CauseCode <= `EX_PRIV;
|
|
xextype <= `EX_PRIV;
|
StatusEXL <= 1'b1;
|
StatusEXL <= 1'b1;
|
EPC <= xpc;
|
pc <= 64'd3;
|
pc <= {TBA[63:13],`PRIV_OFFSET};
|
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRt <= 9'd0;
|
xRt <= 9'd0;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
| Line 3675... |
Line 3744... |
// have occurred in a branch shadow, in which case the
|
// have occurred in a branch shadow, in which case the
|
// current PC isn't valid.
|
// current PC isn't valid.
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (advanceW) begin
|
if (advanceW) begin
|
case(wextype)
|
case(wextype)
|
`EX_RST: begin
|
`EX_NON: ;
|
|
`EX_RST:
|
|
begin
|
pc <= `RESET_VECTOR;
|
pc <= `RESET_VECTOR;
|
case(1'b1)
|
|
wpcv: IPC <= wpc;
|
|
m2pcv: IPC <= m2pc;
|
|
m1pcv: IPC <= m1pc;
|
|
xpcv: IPC <= xpc;
|
|
dpcv: IPC <= dpc;
|
|
default: IPC <= pc;
|
|
endcase
|
|
end
|
end
|
`EX_NMI: begin
|
`EX_NMI,`EX_IRQ,`EX_DBERR:
|
pc <= `NMI_VECTOR;
|
begin
|
|
$display("Stuffing SYSJMP");
|
|
xIR <= {`MISC,19'd0,wextype,`SYSJMP};
|
|
pc <= 64'd3;
|
case(1'b1)
|
case(1'b1)
|
wpcv: IPC <= wpc;
|
wpcv: IPC <= wpc;
|
m2pcv: IPC <= m2pc;
|
m2pcv: IPC <= m2pc;
|
m1pcv: IPC <= m1pc;
|
m1pcv: IPC <= m1pc;
|
xpcv: IPC <= xpc;
|
xpcv: IPC <= xpc;
|
dpcv: IPC <= dpc;
|
dpcv: IPC <= dpc;
|
default: IPC <= pc;
|
default: IPC <= pc;
|
endcase
|
endcase
|
end
|
end
|
`EX_IRQ: begin
|
`EX_OFL,`EX_DBZ,`EX_PRIV,`EX_TRAP:
|
pc <= `IRQ_VECTOR;
|
begin
|
case(1'b1)
|
xIR <= {`MISC,19'd0,wextype,`SYSJMP};
|
wpcv: IPC <= wpc;
|
pc <= 64'd3;
|
m2pcv: IPC <= m2pc;
|
EPC <= fnIncPC(wpc);
|
m1pcv: IPC <= m1pc;
|
end
|
xpcv: IPC <= xpc;
|
default:
|
dpcv: IPC <= dpc;
|
begin
|
default: IPC <= pc;
|
xIR <= {`MISC,19'd0,wextype,`SYSJMP};
|
endcase
|
pc <= 64'd3;
|
|
EPC <= fnIncPC(wpc);
|
end
|
end
|
default: ;
|
|
endcase
|
endcase
|
|
if (wLdPC) begin
|
|
$display("Loading PC");
|
|
pc <= wData;
|
|
end
|
end
|
end
|
|
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// Trailer (TR')
|
// Trailer (TR')
|
| Line 3734... |
Line 3804... |
IDLE:
|
IDLE:
|
if (triggerDCacheLoad) begin
|
if (triggerDCacheLoad) begin
|
dcaccess <= 1'b1;
|
dcaccess <= 1'b1;
|
bte_o <= 2'b00; // linear burst
|
bte_o <= 2'b00; // linear burst
|
cti_o <= 3'b010; // burst access
|
cti_o <= 3'b010; // burst access
|
bl_o <= 5'd8;
|
bl_o <= 5'd7;
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
adr_o <= {pea[63:6],6'h00};
|
adr_o <= {pea[63:6],6'h00};
|
cstate <= DCACT;
|
cstate <= DCACT;
|
end
|
end
|
| Line 3747... |
Line 3817... |
bte_o <= 2'b00; // linear burst
|
bte_o <= 2'b00; // linear burst
|
cti_o <= 3'b010; // burst access
|
cti_o <= 3'b010; // burst access
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
if (ICacheAct) begin
|
if (ICacheAct) begin
|
bl_o <= 5'd8;
|
bl_o <= 5'd7;
|
adr_o <= {ppc[63:6],6'h00};
|
adr_o <= {ppc[63:6],6'h00};
|
cstate <= ICACT1;
|
cstate <= ICACT1;
|
end
|
end
|
else begin
|
else begin
|
bl_o <= 5'd2;
|
bl_o <= 5'd1;
|
adr_o <= {ppc[63:4],4'b0000};
|
adr_o <= {ppc[63:4],4'b0000};
|
cstate <= ICACT2;
|
cstate <= ICACT2;
|
end
|
end
|
end
|
end
|
// WISHBONE burst accesses
|
// WISHBONE burst accesses
|
//
|
//
|
ICACT1:
|
ICACT1:
|
if (ack_i) begin
|
if (ack_i|err_i) begin
|
adr_o[5:3] <= adr_o[5:3] + 3'd1;
|
adr_o[5:3] <= adr_o[5:3] + 3'd1;
|
if (adr_o[5:3]==3'd6)
|
if (adr_o[5:3]==3'd6)
|
cti_o <= 3'b111; // Last cycle ahead
|
cti_o <= 3'b111; // Last cycle ahead
|
else if (adr_o[5:3]==3'd7) begin
|
else if (adr_o[5:3]==3'd7) begin
|
cti_o <= 3'b000; // back to non-burst mode
|
cti_o <= 3'b000; // back to non-burst mode
|
| Line 3774... |
Line 3844... |
tvalid[adr_o[12:6]] <= 1'b1;
|
tvalid[adr_o[12:6]] <= 1'b1;
|
icaccess <= 1'b0;
|
icaccess <= 1'b0;
|
cstate <= IDLE;
|
cstate <= IDLE;
|
end
|
end
|
end
|
end
|
|
//SYSCALL 509: 00_00000000_00000000_00000000_11111110_10010111
|
ICACT2:
|
ICACT2:
|
if (ack_i) begin
|
if (ack_i|err_i) begin
|
adr_o <= adr_o + 64'd8;
|
adr_o <= adr_o + 64'd8;
|
if (adr_o[3]==1'b0) begin
|
if (adr_o[3]==1'b0) begin
|
cti_o <= 3'b111; // Last cycle ahead
|
cti_o <= 3'b111; // Last cycle ahead
|
tmpbuf <= dat_i;
|
tmpbuf <= err_i ? bevect[63:0] : dat_i;
|
end
|
end
|
else begin
|
else begin
|
if (tick[0]) begin
|
if (tick[0]) begin
|
insnbuf0 <= {dat_i,tmpbuf};
|
insnbuf0 <= {err_i ? bevect[127:64] : dat_i,tmpbuf};
|
ibuftag0 <= adr_o[63:4];
|
ibuftag0 <= adr_o[63:4];
|
end
|
end
|
else begin
|
else begin
|
insnbuf1 <= {dat_i,tmpbuf};
|
insnbuf1 <= {err_i ? bevect[127:64] : dat_i,tmpbuf};
|
ibuftag1 <= adr_o[63:4];
|
ibuftag1 <= adr_o[63:4];
|
end
|
end
|
cti_o <= 3'b000; // back to non-burst mode
|
cti_o <= 3'b000; // back to non-burst mode
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
| Line 3799... |
Line 3870... |
cstate <= IDLE;
|
cstate <= IDLE;
|
end
|
end
|
end
|
end
|
|
|
DCACT:
|
DCACT:
|
if (ack_i) begin
|
if (ack_i|err_i) begin
|
adr_o[5:3] <= adr_o[5:3] + 3'd1;
|
adr_o[5:3] <= adr_o[5:3] + 3'd1;
|
if (adr_o[5:3]==3'h6)
|
if (adr_o[5:3]==3'h6)
|
cti_o <= 3'b111; // Last cycle ahead
|
cti_o <= 3'b111; // Last cycle ahead
|
if (adr_o[5:3]==3'h7) begin
|
if (adr_o[5:3]==3'h7) begin
|
cti_o <= 3'b000; // back to non-burst mode
|
cti_o <= 3'b000; // back to non-burst mode
|
